基于边界扫描的板级测试方法研究与应用

【作者】 张乐；

【导师】 戚国庆；

【作者基本信息】 南京理工大学 ， 控制工程， 2012， 硕士

【摘要】 本文以边界扫描法在数字系统板级测试中的应用为主要的研究对象。通过对数字电路的可测性分析,论述了边界扫描法在改善电路可测性设计方面的优点,给出了扫描测试法在电路测试中对故障检测和诊断的具体过程,并对芯片中的扫描单元以及扫描测试的TAP控制器、寄存器、BSDL文件和常用的扫描测试指令进行了分析与研究。同时结合对边界扫描板级测试方法的研究,提出了几种测试总线的配置方式。采用边界扫描法对板级测试中的测试内容进行实际的应用并取得了理想的测试覆盖率报告。首先,通过对电路的可测性分析,结合SCOAP可测性度量给出电路板级测试中网络的可控性与可观性的算法。在可测性度量的前提下提出了改善电路可测性设计的方法,即本文的重点边界扫描测试法,分析了扫描测试在板级故障检测中的优点。其次,通过对边界扫描技术的研究,模拟了扫描单元在测试中的信号加载和采集方式、测试过程中TAP控制器的运行状况以及测试指令和寄存器的相关操作。并对板级测试中的基本故障类型建立了相关的数学模型,详细分析了边界扫描板级测试中的各种待测项的故障诊断与检测过程,对板上IC之间的互连测试和逻辑簇测试进行深入的研究。最后,结合前文可测性设计和板级测试理论与方法的研究对DEMO板进行建模并结合相关信息编写了测试程序,而后展开实际的工程测试,通过对DEMO板人为的设置一些常见的故障来检验扫描测试建模的效果,并最终给出板级测试的整体覆盖率。更多还原

【Abstract】 This paper focuses on the research of the application of boundary scan method in a board testing of the digital system. With the analysis of the measurability in digital circuit, the paper discusses the advantages of improving the electric testability design of the boundary scan method, gives the specific process of the fault detection and diagnosis in circuit test with the scan testing method. Furthermore, this paper analyzes and researches the scanning unit in chip as well as the TAP controller in scan testing, registers, BSDL files and the common instructions in scan testing. Also, the paper combines the research of boundary scan method, puts forward several collocation method in bus testing, provides the actual application of the boundary scan method in a board testing and has obtained the ideal reports of the testing coverage.First, through the analysis of the electric testability and the SCOAP regulation measure, the paper illustrates the controllability and visible algorithm of the network in the electric board test. On the premise of the testability measure, it proposes the better method of the electric testability design, namely the boundary scanning test method of this paper, analyzes the advantages in the board scanning test of the fault detection.Second, by the research of boundary scanning technology, this paper simulates the signal loading of the scanning unit in test and collecting method, the working condition of the TAP controller during the testing and the related operations of registers. Also, the relevant mathematics models of the basic fault types in board test are established, the various kinds of the fault diagnosis and the testing process the boundary scanning in board test are analyzed in detail. In addition, the paper has studied the IC interconnect test and logical test between IC in the boards.Finally, combined with the earlier testability design and the theory research between circuit board test, the paper establishes the demo board as a model and has finished a test program with the relating information, and then spreads the actual engineering test, detects the effect of the common fault in the model scanning test which based on some artificial sets. In the end, the whole coverage rate between circuit board test are supplied.更多还原