收发DBF雷达系统中的软件无线电电路研制

【作者】 倪小康；

【导师】 盛卫星； 马晓峰；

【作者基本信息】 南京理工大学 ， 通信与信息系统， 2012， 硕士

【摘要】 软件无线电技术因其通用性、灵活性、开放性等特点,越来越被广泛应用于无线通信、雷达、电子对抗等领域。它的主要思想是构造一个具有开放性、标准化、模块化的通用硬件平台,并最大限度通过软件实现各种功能。本文根据收发DBF体制雷达系统项目的实际需要,设计并研制了十通道中频收发软件无线电电路,完成了整个电路的软硬件设计和调试测试,包括：原理图设计、PCB版图设计、接口程序设计与调试、电路性能测试以及电路系统功能设计与验证等。所设计电路满足DBF系统指标要求,并已经在实际系统中应用,电路具有如下特性：(1)高速数据采样能力。单板支持10路模拟中频信号输入,ADC电路最高采样率可以达到125MSPS,采用源同步接口通信技术确保高速串行采样数据稳定可靠的传输。目前,单板可实现100MSPS采样率,电路ADC转换有效位数可达9.4位。(2)高速数模转换能力。单板支持10路模拟中频信号输出,DAC电路采用并行差分总线进行数据传输,最高采样率达到500MSPS(实际采样率为250MSPS)。实测结果表明：所输出的30MHz中频模拟信号在1kHz带宽内,相噪≤-120dBc/Hz,带内无杂散动态范围≥60dBFS。(3)高速光纤数据传输能力。单板可以支持双向3.125Gbps x 2的数据传输速率,满足DBF系统超大数据吞吐量的实际需要。(4)强大的数字信号处理和存储能力。单板采用Virtex5系列FPGA芯片作为核心信号处理芯片,可以同时实现十通道数字下变频(DDC)、数字频率合成(DDS)、数据预处理等大量信号处理工作,同时还配有64Mbit DDRII存储器和8Mbit Flash存储器用于数据缓存和非易失性数据存储。更多还原

【Abstract】 Software defined radio (SDR) technique has lots of excellent features, such as versatility, flexibility, openness and has already been widely used in wireless communication, radar, electronic warfare and other fields. The main idea of SDR is to construct an open, standardized, modular generalized hardware platform, and leaves various functions implemented in software as much as possible. In this thesis, in order to meet the demands of the DBF radar system, a ten-channel IF transmitter-receiver SDR circuit has been designed and developed. The main work of this thesis is the hardware and software design of the circuit, including schematic design, PCB design, interface program debugging, performance testing and system function realization. The circuit designed in this thesis has been used in the DBF radar system and satisfy the requirements of system requirement. The main features of the ten-channel IF transmitter-receiver SDR circuit include:1. High-speed data sampling capability. Ten ADC channels are integrated in the circuit. The highest sampling rate of the ADC chips is 125MSPS, using source-synchronous technology to achieve high-speed data transmission. The actual sampling rate of the circuit achieved is 100MSPS with ENOB up to 9.4.2. High-speed digital-to-analog converting capability. Ten DAC channels are integrated in the circuit. The highest sampling rate of the DAC chips is 500MSPS, using parallel differential signal bus to achieve high-speed data transmission. The actual sampling rate using in the circuit is 250MSPS, and the phase noise of the ciruit is less than-120dB/Hz in the bandwidth of 1kHz (IF 30MHz) and the spurious free dynamic range is more than 60dBFS.3. High-speed fiber data transmission capability. Two fiber modules have been integrated in the circuit for serial high-speed bi-direction data communication with data rate up to 3.125Gbps, which satisfy the large data transmission requirements of DBF system.4. Powerful digital signal processing and storage capability. Virtex5 series FPGA has been used as the core signal processor, which achieves 10-channel digital down convert, 10-channel digital signal synthesis and signal pre-processing. Besides,64Mbit DDRII memory and 8Mbit flash memory have been integrated for data caching and non-volatile data storage.更多还原