【作者】 连明超；

【导师】 章专；

【作者基本信息】 浙江大学 ， 电路与系统， 2012， 硕士

【摘要】 在VLSI技术领域的关键问题主要集中在芯片面积、开关速度以及功耗方面。传统CMOS电路的功耗主要来源是开关电流产生的动态功耗,因此其功耗在频率较低时会显现优势,然而随着操作频率的不断增加至大于1GHZ以后,传统CMOS电路的功耗急剧上升,其功耗方面的优势愈发减弱。而且传统的CMOS电路有相当大的内部噪声,这也阻碍了SOC中模拟和数字电路的集成。然而,MOS电流模逻辑(MCML)可以同时满足功耗与频率无关,且提供一个模拟友好环境的需求。目前国内外对MCML电路设计的研究主要集中在二值逻辑的电路特性分析、电路方法设计以及延迟功耗改善等方面,本文从三值逻辑出发进行研究。在深入分析MCML和TG的电路特点后,首先提出将两种结构结合起来进行数字电路设计的思路。该混合结构MCML/TG主要由MCML和TG共同构成,其中MCML结构产生控制信号,TG进行信号的传输。随后,基于该混合结构,论文设计了三值Post代数系统及模代数系统中的各基本电路,并应用所设计的T算子进行全加器的设计。再后,基于该混合结构进行三值D-latch电路的设计；应用所设计的D-latch结构设计主从触发器；进行基于三值时钟的双边沿触发器的设计；分析讨论JKL三值触发器的设计。最后,对所设计的电路进行仿真验证,并利用多值逻辑电路设计的思想来进行二值MCML/TG电路的开关级设计。通过Hspice软件,采用TSMC 0.18um CMOS工艺,供电电压1.8v,对所设计的电路进行仿真,仿真结果分析表明：电路逻辑功能正确；功耗保持MCML结构的优势,基本与频率无关；输入输出高低电平一致,具有较好的电压兼容性；与传统的CMOS电路相比,取得了较大的延迟优化,且保持了简单的电路结构。更多还原

【Abstract】 Recently, VLSI technology has considered chip area, operation speed and power consumption. The traditional CMOS logic circuits dissipate the power only when the load is charging and discharging. Therefore, the power consumption of the CMOS logic circuits is generally small at low frequency. However, by the increasing frequency reaching to 1 GHz, the power consumption of traditional CMOS circuits increase rapidly and the advantage on power consumption will be reduced. In addition, the considerable internal noise of the traditional CMOS circuits hinders the SOC integration of sensitive analog and digital circuits. However, MCML can simultaneously satisfy the requirements of power consumption and speed, and provide a friendly mixed environment.Currently at home and abroad, the researches of MCML circuits mainly focuses on two-valued circuits, such as the analysis of the characteristics of the circuits, circuits designing and improvement of time delay and power consumption, etc. The paper is mainly concentrated on the ternary MCML circuits. Firstly, by analyzing the characteristic of MCML and TG circuits, this paper proposes an idea of designing circuits based on combining the two structures. This mixed structure MCML/TG is mainly composed of MCML and TG, the control signal is produced by MCML and TG is responsible for transmission. Secondly, circuits designing based on the MCML/TG structure in the Post algebraic system and Mode algebraic system is proposed; then using the designed 3-T operator, the paper proposes one kind of full adder. Thirdly, designing of D-latch circuit based on the structure of MCML/TG is proposed and master-slave flip-flop is realized based on the latch; then the paper proposes the double-edge-triggered flip-flop based on ternary clock and discusses the designing of ternary JKL flip-flop analytically. Finally, this paper simulates the designed circuits by Hspice, and using the idea of multi-valued logic designing to conduct the switch-level designing of two-valued MCML/TG circuits. The proposed logic is validated by simulations of Hspice based on the TSMC 0.18 um MOS technology with 1.8v power supply voltage. The simulation results show the power dissipation of the MCML/TG circuits is almost independent of clock frequency, the input and output voltage is consistent, and the propagation delay is improved greatly compared to the conventional CMOS circuits. Moreover, the structure is symmetrical and simple.更多还原