【作者】 王小宁；

【导师】 马义德； 吕兴寿；

【作者基本信息】 兰州大学 ， 电子与通信工程， 2011， 硕士

【摘要】 随着嵌入式系统的发展,基于硬件实现的图像处理技术需求快速增长。软硬件可裁剪是嵌入式系统的特点,高速、实时性是硬件实现的优点,FPGA具有灵活的可编程和可重配置性能,FPGA器件的高集成度和高速处理能力使得用硬件实现图像处理算法成为可能。近年来基于FPGA的图像处理研究成为图像处理领域一个重要的研究方向。基于PCNN和中值滤波器的图像脉冲噪声滤波器算法是本实验室多年来进行图像处理技术研究取得的成果之一。相比Matlab软件实现,将该脉冲噪声滤波器算法移植到FPGA硬件平台实现,具有速度快,性能好等的优点。论文主要进行PCNN脉冲噪声滤波器在FPGA平台上的实现研究。论文设计的基于FPGA的PCNN脉冲噪声滤波器主要包括PCNN噪声检测模块、中值滤波模块、图像显示输出模块和Flash读写控制模块等。在实现过程中解决了以下几个问题：(1)将PCNN结合中值滤波设计的脉冲噪声滤波器在硬件FPGA上实现,主要用PCNN的分类属性来判断噪声点,再用中值滤波来滤除噪声点。(2)在FPGA上实现PCNN脉冲噪声检测时,提出对于高亮度脉冲噪声(盐噪声),使用较高的初始阈值,经过很少的点火次数(1至2次)即可定位出噪声点；而对于低亮度脉冲噪声(椒噪声),只需将图像进行反转,使低亮度变为高亮度,用同样的方法处理即可,这样使迭代次数大为减少。(3)将Flash读写控制和VGA显示控制结合,VGA显示控制模块与滤波器输出连接,使滤波器输出直观在显示器上显示,同时将结果以文件形式保存,便于后期分析处理。更多还原

【Abstract】 With the development of embedded systems, the requirement of hardware-based image processing grows rapidly. Embedded systems have a flexible feature in cutting hardware and software. And hardware implementation possesses the advantages of high-speed and real-time. It is possible that image processing algorithms are implemented in hardware, because FPGA has flexible programmable, reconfigurable performance, high integration and high-speed processing capability. In recent years, FPGA-based image processing becomes an important research direction in the field of image processing.Image filter algorithms for impulse noise based on PCNN and the median filter has been one of the jobs in our laboratory for many years. Compared to the implementation of Matlab software, the implementation of FPGA hardware platform possesses high-speed and good performance and other advantages. In this paper, the PCNN impulse noise filter is implemented on the FPGA platform.In this paper, the design of the filter mainly includes PCNN noise detect module, median filtering module, image display module and control module for read and write(in Flash). The following issues are resolved during the process of FPGA hardware implementation of the filter.(1) The filter based on PCNN and the median filter for impulse noise is implemented in FPGA hardware platform. The noise points are mainly detected by the classification property of PCNN. Then the noise points are filtered by the median filter.(2) When the impulse noises are detected in FPGA, the noises for high- intensity (salt noise) is processed by using a higher initial threshold value, and the noises can be located after firing a few times (1-2 times); while the noises for low-intensity (pepper noise) is detected, only converting low-intensity to high- intensity, the method of processing is the same. So, the number of iterations is largely decreased.(3) It combines the Flash controller for reading and writing with the VGA display controller. And the output of the filter is connected to VGA display output module, so the output results can be displayed on the monitor. At the same time, the results are saved in the flash memory,So that they will be analysed and processed later.更多还原