【作者】 季轩；

【导师】 毛陆虹；

【作者基本信息】 天津大学 ， 微电子学与固体电子学， 2012， 硕士

【摘要】 本文根据阅读器芯片的总体要求,基于SMIC 0.18μm CMOS工艺库,完成了两种数字频率合成器的ASIC设计。其中一种是基于ROM结构的直接数字频率合成器(Direct Digital Synthesizer,DDS);另一种是全数字锁相环(All-Digital PLL,ADPLL)。在DDS芯片设计中,分析了DDS具体应用要求,确定了DDS的系统结构和性能参数,完成了具体子模块的电路设计。其中累加器采用进位链和流水线相结合的方式,提高了工作频率的同时降低了资源占用率;ROM模块应用以正弦函数1/4波形对称性为基础,并结合Hutchison相交分离法的改进压缩算法,压缩率达到49倍,降低了芯片的功耗和面积。基于SMIC 0. 18μm CMOS工艺库完成了DDS芯片的后端物理设计和后仿真。最终,所设计的DDS由Astro生成的版图面积为260×260μm~2,等效两输入门数为1021,平均总功耗为7.79mw,频率分辨率为0.058Hz,输出频率为14.65MHz时,杂散大于70dB,最高输出频率达到100MHz。在ADPLL芯片设计中,电路采用了带有使能控制的环形数控振荡器结构。环形结构分为粗调和精调两部分,具有锁定范围宽、锁定精度高、功耗低的特点,且捕获范围可以根据需要进一步拓宽。与传统锁相环设计不同,本设计基于CMOS标准单元,所有子模块均采用可综合的Verilog HDL代码描述,利于不同工艺间的移植,设计周期和复杂度大大降低。最终,所设计的ADPLL带宽可达72.95MHz-353.66MHz,频率增益为2.47ps,锁定时间小于35个参考时钟周期。输出300MHz时钟时,峰峰值抖动168ps,RMS抖动38.42ps。1.8V电源电压下,DCO功耗范围为0.7mw-1.52mw。最终完成的全数字锁相环版图面积为274μm×274μm,等效门两输入与非门数为4006。更多还原

【Abstract】 Based on the general requirements of the readers , two ASIC designs of frequency synthesizer were implemented with SMIC 0.18μm CMOS technology library in this paper. One is a direct digital synthesizer based on ROM structure ; the other is an all-digital phase-locked loop.In the DDS chip designing ,based on the analysis of specific application requirements of DDS, the paper defined the main performance parameters and system structure, and designed the sub-module circuits . The accumulator module combined the carry line and pipelined architecture together to improve the frequency and reduce the resource utilization; the compression algorithm in ROM module is based on the 1/4 symmetry of sine function and Hutchison algorithm, which made the compression ratio as high as 49 times . What’s more , the power consumption and die area had been greatly reduced . The back-end physical design and simulation had been finished in SMIC’s 0.18μm CMOS process. The finished area of the DDS layout is 260×260μm~2, and the equivalent gate count is 1021. The average power consumption is 7.79mw. The frequency resolution is 0.058Hz ; when the output frequency is 14.65MHz, the stray is more than 70dB. The highest operation frequency of DDS is up to 100MHz .In the ADPLL chip designing, the ADPLL had a ring digital-controlled oscillator composed by enabled units, with the ring structure divided into two parts in terms of the coarse tuning part and the fine tuning part. It included the characteristic of wide locking range, high locking resolution, and low power consumption. What’s more, the locking range can be further expended according to the demand. Different from the traditional design, this design was based on CMOS standard cells and used synthesizable Verilog HDL for sub-modules description, so it could be easily implanted to different processes, and both the design time and complexity could be reduced. This ADPLL can operate from 72.95MHz to 353.66 MHz, the resolution is 2.47 ps , the locking time is smaller than 35 cycles. When the output frequency is 300MHz ,the peak-to-peak jitter is 168ps and RMS jitter is 38.42ps. With a 1.8V power supply, the proposed DCO has a power consumption range from 0.7mw to 1.52mw. The finished area of the ADPLL layout is 274μm×274μm, and the equivalent gate count is 4006.更多还原