【作者】 蔡大伟；

【导师】 许洪光；

【作者基本信息】 哈尔滨工业大学 ， 信息与通信工程， 2011， 硕士

【摘要】 存储器的性能在很多数字化系统中占据着重要的地位,是决定系统性能的关键之一。DDR SDRAM具有容量大、读写速度快、运行稳定性强、技术成熟以及高性价比等优点,得到了广泛的应用。因而对DDR SDRAM存储控制器的研究具有重要的意义。本文研究设计的DDR SDRAM控制器主要应用于PXI高速虚拟数字示波器。由于该示波器对数据的存取速度有着很高的要求,读写速度要求达到2Gbyte/s。虽然DDR SDRAM可以进行高速数据的读写,但是由于本身时序及控制操作的复杂性,要想达到2Gbyte/s的读写速度,就对控制器的设计提出了更高的要求。传统的DDR SDRAM控制器一般采用MCU,DSP实现,由于它们本身集成的资源有限,对于设计复杂的数字系统,实现高速存储就会很困难。为了达到2Gbyte/s的读写速度,本文提出了新的控制器设计思想,即用FPGA对DDR SDRAM的四个BANK进行循环控制,同一时刻保证会有一个BANK是在存取数据,通过对四片DDR SDRAM同时进行如上操作,进而达到2Gbyte/s的数据读写速率。本文主要进行了如下工作,首先对DDR SDRAM控制器设计的基本理论和关键技术进行了研究和分析。并对DDR SDRAM的控制器的硬件部分进行了设计实现。接着对DDR SDRAM控制器的控制部分用硬件描述语言VHDL,采用自顶向下(Top-To-Down)的设计思想和模块化的设计方法,对控制器进行模块化设计,最后对设计进行仿真,并对硬件电路进行了测试验证。验证得到的信号仿真波形显示本控制器的设计满足本设计系统的需要。更多还原

【Abstract】 The performance of memory is important in many digital systems, it mostly determines the system performance. The DDR SDRAM characterized by large memory capacity, high access speed, good stability, mature technology and high cost-effective, and it has been widely used in many storage systems.In this paper, the DDR SDRAM controller is mainly used in the PXI digital virtual oscilloscope, and it requests high speed data access, which needs to achieve 2Gbyte/s.Although the DDR SDRAM has High-speed access rate, the timing and control operation are very complex, so it needs a higher request to the design of the controller. The design of traditional DDR SDRAM controller is mostly based on MCU and DSP, but it is difficult to achieve high-speed storage in the complex digital systems for their own limited resources which have been integrated inside. And for that reason, this paper presents a new controller design; it controls the four BANK of DDR SDRAM circularly with FPGA at the same time, and ensures that there will be one BANK at least in reading or writing process. Then do the same operation to four DDR SDRAM at the same time, and eventually we will reach the request of rate about 2Gbyte/s.The paper has done the following work. Firstly, it has researched the basic theories and key technologies of DDR SDRAM controller design. Secondly, it has designed the hardware part of the controller, and it is mostly about the peripheral circuits. Thirdly, it has completed the design about control section of DDR SDRAM controller with hardware description language VHDL, which used the design idea of Top-To-Down and modular design method. And finally it has done simulation to the design and tested the hardware, and the wave of the simulation shows that the design completely meets the request of the design system.更多还原