【作者】 吴晓爽；

【导师】 林凌；

【作者基本信息】 天津大学 ， 精密仪器及机械， 2010， 硕士

【摘要】 随着当今科学技术的不断发展,现代信号处理技术的应用对微弱信号检测提出了更高的要求。如何将噪声淹没的微弱信号检测出来,并获得正确的数据,是一个十分重要的课题。微弱信号检测技术的方法很多,对于正弦信号而言,锁相检测是众多方法中非常有效的手段。本文在对微弱信号检测的基础理论与锁相检测算法研究的基础上,做了如下的工作:对于微弱信号一般需要尽可能高的检测分辨率,而过采样技术能够在一定条件下提高微弱信号检测的有效分辨率,对过采样技术进行了梳理。通过仿真和实测实验证明了采样速率每增加4倍,可以使信噪比提高6dB,相当于使ADC提高了一位分辨率。针对经典的数字锁相检测,由于要进行大量的乘法运算而导致计算速度慢的问题,本文提出了一种全新的数字锁相检测的快速算法。该快速算法对所需检测频率信号每周期采样4点,利用其正交参考信号的值仅为0、-1和1来去除所有的乘法和部分的加法运算,大幅度地减小了运算量。仿真和实测实验结果表明,对于周期数为N的采样数据计算,可减小8N次的乘法运算和4N次的加法运算。为了提高快速算法的精度,提出了基于过采样的快速算法。结合了过采样和快速算法的优势,采用平均下抽样技术将采样频率还原为4倍于原始信号的频率。引入修正因子改善计算出的幅值的精度,理论上完全消除了误差。仿真与实测实验结果表明,这种全新的基于过采样的快速算法既有过采样和锁相检测的高精度,又具备很高的速度。针对现有的数据采集常用单片机或DSP作为主控制芯片,但是普通单片机的运行速度不高,经常成为数据通道上的瓶颈,使模数转换芯片的性能无法完全发挥;尽管DSP芯片运行速度快,但其价格和易用性却比不上FPGA的问题。本课题利用Virtex-5 FPGA系列的XC5VLX110T实现数模转换芯片AD8802、模数转换芯片AD7760和UART16550IP核的控制,实现高速采集的全新数字锁相算法。更多还原

【Abstract】 With the continuous development of science and technology, the application of modern signal processing techniques proposed a higher requirement for detection of weak signal. How to detect the weak signal from the noise and obtain the right data is a very important issue.Comparing to other ways, the phase-locked detection is a more effective way for the sinusoidal signal. In this paper, the following works have been done based on the weak signal detection theory and lock detection algorithm:The weak signal detection generally requires the highest resolution,while the over-sampling technology can improve the effective resolution of weak signal detection under certain conditions, and the oversampling technique was combed. The simulation and experimental results show that while the sampling rate increases by 4 times, the SNR can be improved by 6 dB, which means the ADC increases 1 bit.For the classic digital lock detection, due to a lot of multiplication, the calculation speed is low. A new fast-speed digital lock detection algorithm was proposed in this paper. The fast algorithm is as follows: four samples are taken per period from the frequency signal testing required, the orthogonal reference signal values are set to be 0、-1 and 1 to remove all the multiplication and parts of addition, which can greatly reduce the computation. Simulation and actual experiment results showed the calculation for the sampling data of cycles N can be reduced multiplications by 8N times and additions by 4N times. In order to improve the accuracy of the fast algorithm,the fast algorithm based on the oversampling was proposed. The algorithm which takes the advantages of oversampling and fast algorithm used the average down-sampling technology to reduce the sampling frequency to 4 times of the frequency of the original signal. The modification factor was introduced to improve the calculation accuracy of the amplitude,by which the error can be eliminated completely in theory. The results of the simulation and actual experiment showed that the new fast-speed algorithm based on oversampling was valid not only with the high precision of oversampling and lock-in detection,but also with a high speed.Today, microcontroller or DSP is often used as the main controlling chip, but the running speed of the microcontroller is not high, which always become a bottleneck on the data channel, so that the analog-digital conversion chips can not play their best performance;Although DSP chips can run faster, but its price and feasibility is worse than FPGA. The subject used the XC5ULX110T of Virtex-5 FPGA family to control the AD8802 of the digital-analog conversion chip、AD7760 of the analog-digital conversion chip and UART16550 IP nuclear to realize the new digital lock algorithm of a high-speed acquisition.更多还原