【作者】 尹帅；

【导师】 喻明艳；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2010， 硕士

【摘要】 随着电路系统数字化程度不断提高,模数转换器作为模拟信号与数字信号的接口电路,其作用也越来越重要。在诸多类型的模数转换器中,流水线模数转换器以其高速度和高精度而得到广泛应用。传统流水线模数转换器以模拟电路为主,其功耗、速度和精度之间存在严格的制约关系。而数字辅助流水线模数转换器采用简单的模拟电路代替复杂的数字电路,即在流水线的第一级采用简单的开环放大器,降低功耗,提高速度,在数字校正部分使用精确的校正算法校正开环放大器产生的非线性误差,改善精度,从而有效解决了传统流水线功耗、速度和精度之间严重的制约关系。设计了12位40MS/s数字辅助流水线ADC的关键单元。首先分析系统整体结构,在考虑开环放大器非线性因素的基础上,建立系统的Verilog-A模型,验证校正方法的正确性。使用Cadence中的Spectre仿真软件,对没有数字校正的系统和带有数字校正的系统进行静态参数仿真,其INL从(-18LSB, 0.4LSB)降低到(-0.4LSB, 0.2LSB),DNL从(-0.5LSB, 0.4LSB)降低到(-0.2LSB, 0.2LSB)。并对带有数字校正的系统进行动态参数仿真,得到其SFDR达到86dB,SNDR达到72dB。另外,使用SMIC 0.35μm混合信号CMOS工艺,设计流水线第一级电路,按照建模的方法,在子ADC的最后一位加入伪随机信号,仿真结果表明在电路上实现了后台数字校正算法所要求的双余量曲线。更多还原

【Abstract】 As an interface circuit of analog signal and digital signal, analog to digital converters get more and more important with the digitalize of the system. Pipeline ADC is applied broadly as its fast speed and high precision. However, a majority of the conventional pipeline ADCs are analog circuits, which have the restriction of power, speed and precision dramatically. To solve the problem and push up the advantages of digital circuits, simple analog circuits and complex digital arithmetic are used to transform the difficulty of ananlog circuit design to the complexity of the digital arithmetic. An open-loop amplifier is used in the first stage of the pipeline ADC to reduce the power and increase the speed. At the same time, accurate arithmetic is used in digital correction to correct the nonlinearity induced by the open-loop amplifier, which improves the precision. The method can relax the relationship between power, speed and precision effectively.A 12-bit 40MS/s digitally assisted pipeline ADC is designed. First, Verilog-A is used to model the system to verify the digital correction with the nonlinearity of open-loop amplifier. Spectre in Cadence is used to simulate the system. Comparing the results of the system without and with digital correction, the INL falls from (-18LSB, 0.4LSB) to (-0.4LSB, 0.2LSB) and the DNL falls from (-0.5LSB, 0.4LSB) to (-0.2LSB, 0.2LSB). Simulating the system with digital correction dynamically, the SFDR is 86dB and the SNDR is 72dB. Moreover, SMIC 0.35μm mix signal CMOS technology is used to design the circuit of the first stage. In terms of the modle built forward, RNG is added to the last bit of the thermometer codes. The simulation shows that the two-residue plot fulfilling the digital correction can be realized in the form of schematic.更多还原