【作者】 姜建军；

【导师】 刘渝；

【作者基本信息】 南京航空航天大学 ， 信号与信息处理， 2010， 硕士

【摘要】 随着现代雷达技术的不断发展,电子侦察接收机面临的电磁环境日益复杂多变,发展宽带化、数字化、多功能、软件化的电子侦察接收机是一项重要的任务。数字信道化接收机具有大监视带宽、高灵敏度、大动态、高频率分辨率、高截获概率和多信号处理能力等诸多优势,是应用广泛的一类电子战接收机。本文给出了一种基于多相滤波的宽带数字信道化结构,在一定信噪比的条件下,利用该结构的信道化接收机处理ADC输出数据,检测信号、测频并给出脉冲描述字。首先,本文在信道化基本结构基础上,推导出一种基于多相滤波的数字信道化的高效结构,分析了数字滤波器组特征,合理设计滤波器带宽和信道化抽取比,可完成监视带宽内无缝连接,并较好地抑制兔耳效应,以确保全概率接收。针对该结构进行了计算机仿真,对其性能进行了深入分析。然后,讨论了几种常见的信号检测方法和测频方法。结合具体的硬件平台,提出一种幅度检测加双谱线测频的编码方法,可以很好地解决相邻信道间虚假信号输出问题,同时提高测频精度。最后,研究了在单片FPGA上实现信道化接收机的方案,系统的处理带宽为1GHz,解决了高速ADC与低速信号处理器FPGA之间的矛盾,并在Xilinx的XC4VSX55芯片上实现了对两个同时到达信号的检测,实现了对脉冲流的脉冲到达时间、脉冲宽度和信号瞬时频率等参数的实时高精度测量,以脉冲描述字的形式输出。该设计是针对FPGA的硬件实现方法,其系统结构简单,测量速度快、精度高,满足对脉冲参数测量高精度、实时性的要求。更多还原

【Abstract】 The continuous developments of modern radar technology and the consequent more complicated electromagnetic environment have made it crucial to design wideband, digital, multifunctional software electronic reconnaissance receiver. Digital channelized receiver is an EW receiver that provides wideband frequency coverage, high sensitivity and dynamic range, high intercept probability and simultaneous signal detection and fine frequency resolution. In this dissertation, a structure based on polyphase decomposition is introduced, and how to detect signal and get PDW under the conditions of certain signal to noise rate when adopting the data output of the ADC is mainly discussed.First of all, one of the efficient architecture of digital channelized receiver based on polyphase filters is built in comparison with the basic architecture. The characteristics of polyphase filters are analyzed and the rabbit ear effect is preferably restrained as well. In order to have continuous coverage across of the IBW, adjacent channel responses are overlapped. The computer simulations experiments were done, and then the performances were analyzed deeply.Secondly, two kinds of signal detection and frequency measurement methods are discussed. Then one simple method based on amplitude comparison and Rife method is proposed. The false outputs can be eliminated and frequency-measurement accuracy can be highly improved by using this operation.Finally, a realization of channelized receivers based on poplyphase filtering on one FPGA chip is given in this paper. This design covers 1GHz bandwidth .This method resolves the contradiction between the high-speed ADC and low-speed digital signal processor (FPGA). The design can deal with both real-time signals and we introduce how to get the TOA, PW and IF based on Xilinx XC4VSX55. This method refers to performance on FPGA,and the system is simple, high speed and precision.更多还原