【作者】 孙川；

【导师】 王友仁；

【作者基本信息】 南京航空航天大学 ， 测试计量技术及仪器， 2010， 硕士

【摘要】 随着半导体工艺与集成电路的不断发展,数字电子系统的集成度越来越高,它在生命周期中发生故障的可能性也随之增大。因此,数字电子系统的容错能力逐渐受到了人们的重视。可重构阵列具有可重复编程、功能灵活、集成度高、开发周期短与研发成本低等优点,在电子系统设计中已经得到了广泛应用,它的出现为电子系统的容错提供了更为灵活的方法。目前,可重构阵列的自测试与容错技术已经成为研究热点之一。本文主要研究了可重构阵列的自测试与容错技术,论文的主要研究工作如下:(1)通过改进设计使可重构阵列有两种工作模式:普通工作模式和故障自测试工作模式。其中,当可重构阵列处于对安全性要求较高的条件下时,可以拉低测试使能信号使其工作在自测试模式。可重构阵列采用在线循环自测试方法,故障测试时并不影响阵列执行正常的逻辑功能。(2)针对可重构阵列冗余资源利用率低以及时间开销大等问题,本文设计了两层容错机制:1)在测试到故障后,首先在细胞单元内部以空闲的基本逻辑单元为重构对象完成第一层容错,此过程不需要内建容错处理单元的参与,实现自主容错;2)当细胞单元内部没有空闲的基本逻辑单元时,通过调用内建容错处理单元发出控制命令,以距故障细胞单元最近的空闲细胞单元取代故障细胞单元来实现第二层容错。(3)本文最后以六位并行乘法器和六位并入串出移位寄存器为例实现在阵列上的映射,对其仿真并下板测试,验证了可重构阵列的自测试与容错能力,并和其它可重构阵列容错技术的容错能力、冗余资源利用率和容错时间进行了分析对比,说明本文设计结构具有容错性能好、资源利用率小和时间开销小等方面的优势。本课题研究工作受国家自然科学基金(60871009)和航空科学基金(2009ZD52045)的资助。更多还原

【Abstract】 With the continuous development of the semiconductor technology and the integrated circuit, digital electronic system are more integrated, and its possibility of failure in the life cycle is even greater. Therefore, people gradually start to attach importance to the fault-tolerant ability in digital electronic system. The reconfigurable array has the characteristic of a repeatable programming, functional flexibility, high integration, short development cycle and low cost of research. The reconfigurable array has been widely used in the design of electronic system, It also provides a more flexible approach for fault-tolerant electronic system. Currently, self-test and fault-tolerant technology of reconfigurable array has become a research hot spot.This paper mainly studies the self-test and fault-tolerant technology of reconfigurable array, major research are as follows:(1) By improving the reconfigurable array, there are two operation modes: normal operation mode and self-test operation mode. When the reconfigurable array is in a higher degree of security conditions required, you can pull down test enable signal to make it work in self-test mode. It uses online circular self-test method, fault self-test doesn’t affect the implementation of normal logic functions.(2) The reconfigurable array has the low utilization rate of resources and needs more time, this paper designed a two-level fault-tolerant method: 1) When the fault has been tested, first, using the spare BLE to achieve the first-level fault-tolerant, this process doesn’t need the participation of build-in fault-tolerant processing unit; 2) When the cell unit lacks the spare BLE, by calling the build-in fault-tolerant processing unit to issue control commands, the nearest spare cell unit will replace the fault cell unit to achieve the second-level fault tolerance.(3) This paper exemplifies 6-bits parallel multiplier and 6-bits string out shift register, which are simulated and downloaded to FPGA board, to verify the fault-tolerant ability of reconfigurable array. By analysing and comparing with other reconfigurable arrays in fault-tolerant ability, resource utilization and fault tolerance time, the results show that the structure designed in this paper improves the resource utilization and reduces the time overhead.The work presented in this paper has been funded by National Natural Science Foundation of China (60871009) and Aeronautical Science Foundation of China (2009ZD52045).更多还原