钯纳米晶的自组织生长及其电荷存储效应的研究

【作者】 黄万一；

【导师】 丁士进；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2011， 硕士

【摘要】 随着半导体工艺技术的不断发展,非挥发性快闪存储器的集成密度越来越高,存储单元特征尺寸不断减小,因而传统的多晶硅浮栅快闪存储器正面临着严峻的挑战,如隧穿氧化层的减薄导致数据保存能力退化等。而基于分离电荷存储的非挥发性存储器,可以采用更薄的隧穿氧化层同时保持着良好的数据保留特性,由此可以带来更低的编程/擦除电压和更快的编程/擦除速度,是下一代快闪存储器最理想的解决方案之一。基于上述思想,本论文研究了金属Pd纳米晶的制备方法以及它作为电荷存储中心的电学性能的研究。具体内容包括以下几个方面：(1)采用磁控溅射金属薄膜和淀积后快速热退火(RTA)的方法,对在A1203介质薄膜上生长钯(Pd)纳米晶的工艺进行了研究。论文首先对影响钯金属薄膜淀积速率的因素进行了实验研究,找到了较理想的淀积速率。随后,较系统地研究了退火温度、退火时间、RTA升温速率等对钯纳米晶生长的影响。结果表明,在磁控溅射靶功率为10W,Ar气流量为45sccm,淀积时间为230s的淀积条件下,所得到的初始薄膜更有利于纳米晶的生长。此外,在RTA形成钯纳米晶的过程中,随着退火温度的升高,钯纳米晶的尺寸变大,密度降低。通过工艺优化,发现理想的RTA条件为退火温度850℃,退火时间15s,升温速率为20℃/s。在该条件下,所得到的钯纳米晶的平均直径为10nm,密度为4×1011cm-2。另一方面,本论文还对传统SiO2介质上钯纳米晶的生长特性进行了研究,揭示了在溅射功率为10W,Ar气流量为45sccm,淀积时间为400s的淀积条件,以及退火温度750℃,退火时间15s和升温速率为20℃/s的RTA条件下,获得了平均直径为12nm、密度为1.5×1011cm-2的钯纳米晶。(2)采用反应共溅射后退火技术制备了嵌于TiO2高介电常数(High-k)介质薄膜的Pd纳米晶。首先,通过在O2与Ar混合等离子体环境下共溅射金属Pd与Ti靶,以得到PdTiO介质薄膜,然后将该复合薄膜在N2氛围下经过高温快速热退火,从而形成内嵌Pd纳米晶的TiO2薄膜。借助X射线衍射(XRD)、高分辨率透射电镜(HRTEM)和X射线光电子能谱(XPS)等分析手段,系统地研究了不同的Pd/Ti溅射功率、不同的RTA条件对Pd纳米晶的形成过程、化学组分和材料结构等特性的影响。结果表明,TiPdO薄膜中Pd相对含量越高,退火后所形成的Pd纳米晶颗粒越大。而且,随着快速热退火温度的升高,Pd纳米晶颗粒逐渐变大。同时,XPS数据分析表明,共溅射PdTiO初始薄膜含有PdO2、PdO、TiO2、Ti2O3成份；经过600℃快速热退火后,PdO2发生了完全分解,PdO发生了部分分解,同时伴随着Ti2O3到TiO2的转化过程的发生。当快速热退火温度上升到900℃时,PdO继续发生分解,且Pd纳米颗粒直径变大。(3)制作了以原子层淀积A1203为隧穿层与阻挡层,以内嵌Pd纳米晶的Ti02薄膜为电荷俘获层的MOS电容结构,并采用金属Pd为电极。其电学测试结果显示,该MOS结构的C-V滞回窗口随着扫描电压范围的增大而不断增大,表明了内嵌于TiO2薄膜中的Pd纳米晶具有很好的电荷俘获特性。对于内嵌Pd纳米晶的MOS电容器,当扫描范围为±3V时,该电容表现出的C-V滞回窗口(AVFB)只有-0.5V。随着扫描电压的增大,滞回窗口不断增大。当扫描电压范围为+9V时,C-V滞回窗口达到(ΔVFB) 8.2V。有趣的是,当扫描电压范围从±3V增加到±5V时,平带电压的偏移量从0.5V突变到3.1V。而且,当正向扫描时,随着初始扫描电压的增加,MOS电容的平带电压VFB显著地向负电压方向移动,且没有出现饱和现象。然而,对于负向扫描时,随着初始扫描电压(正偏置)的增大,所得平带电压向正方向偏移,但很快达到饱和。换句话说,当初始扫描电压≤7V时,所得平带电压VFB随着初始扫描电压的增加有比较明显的正方向偏移。然而,当初始扫描电压≥9V时,所得平带电压VFB基本不随初始扫描电压的增大再向正方向偏移,即电子存储达到了饱和。这是由于电荷隧穿机制在低压下主要是直接隧穿,而在高压下则为F-N隧穿；而对于空穴来讲,由于金属Pd与阻挡层介质的价带偏移(band offset)较大,以致于空穴在高压下也不可能发生F-N隧穿,而仍然以直接隧穿为主。同时,实验结果表明当电压恒定为+9V时,所施加脉冲宽度为10ns就能够使MOS电容产生-2V的平带电压偏移；当施加脉冲宽度恒定为10ms时,脉冲电压为+7V就能够使MOS电容产生-2V的平带电压偏移。通过对不同脉冲电压和脉冲宽度下有效注入电荷密度和注入速度的计算,经计算得到最大注入电荷密度约为8×1011cm-2。同时,电荷注入过程基本发生在初始阶段,且有效电荷注入速度在初始的10ns范围内约为6×1012cm-2μs-1。实验表明这种结构的纳米晶存储器将会有很大的应用前景。更多还原

【Abstract】 With the development of semiconductor technology and downscaling of the device feature size, the conventional poly-silicon floating gate flash memories are facing a severe challenge that scaling of the tunneling oxide thickness will degenerate retention characteristics. Embedded nonvolatile flash memory devices based on discrete charge storages have been considered as one of the most promising candidates due to their improved retention characteristics in the case of a thinner tunneling layer, and faster program/erase (P/E) speed under lower operating voltages. Therefore, the fabrication process of Pd nanocrystals and its electrical characteristics as the charge-trapping center are presented in this thesis and the involved physical mechanisms are also discussed. The details include the following sections:(1) The formation of Pd nanocrystals on Al2O3 layer has been investigated by rapid thermal annealing (RTA) of sputtered Pd film. Firstly, the influence of various factors on the deposition rate of the initial Pd film has been studied, and the ideal depostition conditions have thus been achieved. Subsequently, the thesis has investigated comprehensively the influence of RTA temperature, annealing time, and RTA ramp rate on the growth of Pd nanocrystals. The results show that Pd nanocrystals are prone to be formed under conditions such as:magnetron sputtering target power of 10W, an Ar flow rate of 45sccm, a deposition time of 230s. Furthermore, the size of the resulting Pd nanocrystals increases and the nanocrystal density decreases with increasing the annealing temperature. The optimized annealing conditions are as follows:an annealing temperature of 850℃, an annealing time of 15 s, and a RTA ramp rate of 20℃/s. Accordingly, Pd nanocrystals with an average diameter of 10nm, and a particle density of 4×1011 cm-2 have been obtained. In addition, the growth of Pd nanocrystals on the conventional SiO2 film has also been investigated. It is shown that the process parameters such as target power of 10 W, an Ar flow rate of 45 sccm, a deposition time of 400 s, an annealing temperature of 750℃, an annealing time of 15 s, and a RTA ramp rate of 20℃/s can result in the Pd nanocrystals with an average diameter of 12 nm, and a density of 1.5×1011 cm-2.(2) Pd nanocrystals embedded in TiO2 high-k dielectrics have been prepared by reactive co-sputtering and RTA technique. The PdTiO films are firstly deposited by reactive co-sputtering in a plasma mixture of O2 and Ar, and then treated by rapid thermal annealing (RTA) at high temperatures in N2. As a result, the Pd nanocrystals are formed spontaneously embedded in titanium oxide by means of decomposition of Pd oxides and subsequent growth of Pd nuclei. The influence of Pd/Ti power ratio and RTA process on the formation process, the nanostructure and chemical composition of Pd nanocrystals have been investigated by the method of XRD, EDS, HRTEM, and XPS. The experimental results indicate that the TiPdO film with a high content of Pd is inclined to produce big nanocrystals. Furthermore, the higher the RTA temperature, the bigger the Pd nanocrystals become. In addition, our analyses of the x-ray photoelectron spectroscopy spectra reveal that PdO, PdO2, Ti2O3, and TiO2 coexist in the as-deposited film, and the RTA at 600℃leads to decomposition of the entire PdO2 and partial PdO, together with the growth of Pd nanocrystals. At the same time, the released oxygen oxidizes fully Ti2O3 into TiO2 during the decomposition. As the RTA temperature is increased up to 900℃, more and more PdO is decomposed and the Pd nanocrystals become bigger and bigger.(3) The MOS capacitors with Pd nanocrystals embedded in TiO2 film as the charge trapping layer has been fabricated, together with the ALD Al2O3 layer as the tunneling and blocking layers, and metal Pd as the electrode. The electrical measurement results show that Pd nanocrystals embedded in TiO2 film as the charge trapping layer result in good memory effect. When the sweep voltage range is±3 V, a memory window of 0.5 V can be observed. And the amount of the flatband voltage shift (ΔVFB) increases further with enlarging sweep voltage range and comes to about 8.2 V at±9 V. It is interesting to find that the memory window (i.e.,ΔVFB) increases abruptly from 0.5 to 3.1 V with raising the sweep voltage range from±3 V to±5 V. What’s more, with reference to the forward sweep, the resulting VFB shifts distinctly toward a negative bias with increasing the gate sweeping voltage and no saturation of hole-trapping is found. As far as the backward C-V sweep, it is found that the resulting VFB shift obviously in the direction of the positive bias with increasing the sweep voltage and the saturation is also found. In other word, the resulting VFB shifts obviously in the direction of the positive bias with increasing the sweep voltage when the sweep voltage≤7V. However, when the sweep voltage≥9V, it shifts hardly, which indicates the saturation of electrons-charging. This is because the charges injection under low voltage is dominated by direct tunneling mechanism and F-N tunneling mechanism under high voltage. As far as the holes, however, the valence band offset of Pd and the controlling oxide is so large that F-N tunneling for holes though the controlling oxide to the electrode is unlikely to occur, so direct tunneling still dominates. It is also observed that when the stress voltage is equal to+9 V, the pulse width of 10ns could result a VFB shift of～2 V. When the pulse width is kept at 10ms, a stress voltage of+7 V could result in a VFB shift of～2 V. Finally, the maximum effective injected charge density is calculated to be about 8×1011 cm-2. Meanwhile, the basic process of the charge injection occurs in the initial stage, and the effective charge injection rate is about 6×1012 cm-2μs-1 in the case of 10-8 s, indicating a great potential for this memory structure.更多还原