音频低电压连续时间Sigma-Delta模数转换器研究与实现

【作者】 董一枫；

【导师】 许俊；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2011， 硕士

【摘要】 本文针对助听器的应用,依托国家863计划重点项目,设计了一款1-V、16-bit、20-KHz信号带宽的连续时间Sigma-Delta ADC。和采用开关电容的离散时间Sigma-Delta ADC相比,连续时间方案有着明显的低功耗优势,并且还有固有的抗混叠特性。本设计的调制器采用单比特量化,128倍过采样,四阶前馈结构,用有源RC积分器来实现,设计了在低电压下工作的两级class A/AB型运放,引入了一个固定延时吸收量化器信号相关延时。数字降采样滤波器采用梳状滤波器级联两级半带滤波器的结构,其中梳状滤波器采用8-4级联方式实现32倍降采样,所有子滤波器都为FIR滤波器,采用了采样转置和多相采样技术,以降低了功耗。本文设计的Sigma-Delta调制器采用SMIC的0.13-μm Mixed Signal CMOS工艺实现,芯片的核心面积为0.64×0.361mm2,功耗约为110μW。后仿真结果表明,芯片在1-V电源电压下,5.12 MHz采用时钟下,20 KHz带宽范围内,SNDR可以达到最高108 dB, SFDR最高可以达到110.5 dB。更多还原

【Abstract】 Basing on the National 863’s Plan, this paper presents aⅠ-Ⅴ,16-bit,20-KHz bandwidth continuous-time Sigma-Delta modulator for hearing-aid applications. Compared with discrete-time sigma-delta modulatours implemented with switch-capacity technology, continuous-time sigma-delta modulators have the advantage of a lower power consumption and inherent anti-alias filtering. The presented modulator utilizes an 1-bit quantization 4th order feed-forward loop with a OSR of 128. It is implemented in active-RC integrators. A 2-stage class A/AB amplifier is designed to meet the low voltage supply requirement. A constant delay is introduced to solve the signal-dependent delay. The digital decimation filter is realized with a cascade combination of a comb filter and two half-band filter. The comb filter is implemented as a 8-4 cascade structure to realize a down sampling rate of 32. All the filter is FIR filter with utilizing sampling transposing and poly phase sampling technologies, so that the power consumption can be reduced.The modulator is realized by SMIC0.13-μm Mixed Signal CMOS process, the core chip size is about 0.64x0.36 mm2 and the power consumption is about 110μW. The chip can work underl V, clocking at 5.12 MHz with a bandwidth of 20KHz. The modulator can achieves a peek SNDR of 108 dB and a peek SFDR of 110.5 dB.更多还原