2.7GHz高速接口电路的ESD电路设计及仿真分析

【作者】 陈景阔；

【导师】 李平； 崔自中；

【作者基本信息】 电子科技大学 ， 软件工程， 2011， 硕士

【摘要】 随着技术的进步,工艺的改进,一方面集成电路的集成度越来越高,另一方面芯片之间数据传输的速度也越来越快。工艺的进步,使得芯片的尺寸越来越小,介质氧化层越来越薄,结深越来越浅,而静电并不会因为这些改变而减弱,从而会造成芯片承受静电的能力越来越差。在每年失效的大量芯片中,由静电放电所引起的占据了一半的比例。因此集成电路的可靠性在很大程度上依赖于静电放电保护电路的性能。对于深亚微米的集成电路设计来说,设计出有效的ESD保护电路变得尤为重要。半导体器件的制造和芯片级的测试,极大程度上依赖于精密的设备。众所周知,微电子行业的相关设备价格昂贵,测试需要的各种损耗品也价格不菲,而借助软件对器件进行模拟分析,可以快速精确的得到器件的各种性能,而且可以对器件结构进行优化,以获得更加理想的特性,从而降低研发费用。常用的有电路级仿真工具Hspice和器件级仿真工具MEDICI。基于高速串行SerDes接口,设计出了具有高速性能的ESD保护电路。采用台积电(TSMC)0.13μm工艺,实现了一种既能满足2.7Gbps高速的要求,又能满足耐压达2000V的ESD保护电路。在设计中对于高速的要求是通过建立Hspice模型,使用Hspice在正常输入信号的情况下进行仿真,在高速方面得到了理想的结果;对于耐压的要求,则是通过二维器件仿真工具MEDICI从器件角度来仿真验证的。通过建立器件模型,并对器件模型进行优化,对于人体模型达到了耐压2000V的要求。本文设计的ESD保护电路既实现了2.7Gbps的高速要求,也实现了耐压2000V的要求,满足了芯片正常的使用的要求。更多还原

【Abstract】 With the development of technology and improvement of process, on the one hand, the integrated level of ICs becomes higher and higher; on the other hand, the data rate between chips becomes faster and faster .The advancement of progress leads to smaller chips, thinner gate oxide, shallower junction depth.Unfortunately ,the electrostatic will not be weakened because of these changes.As a result,the ablitity of electrostatic that Ics should bare is getting worse.We can see from the statistics,the proportion of failure chips caused by electrostatic in a large number of chips per year accounted for half of the ratio. Therefore, the reliability of integrated circuits is heavily depend on the performance of ESD protection circuits. For deep sub-micron integrated circuit design, the design of effective ESD protection circuit has becomes particularly significant.The manufacture of semiconductor devices and chip-level testing are greatly depend on sophisticated equipment, we all know, the microelectronics industry-related equipments are too expensive,and the loss products that testing should need are also too expensive, so we can emply software to simulate and analyse the devices and circuits, As a result,the various paraters of the device properties can be quickly and accurately acquired.Furthermore,we can optimize the device structure to obtain more desirable properties,witch can reduce development costs. Commonly used circuit-level simulation tools and device-level simulation tools are Hspice and MEDICI.Based on the design of high-speed SerDes interface, the ESD protection circuit with high performance is designed. The protection circuit based on TSMC (TSMC) 0.13μm process,the ESD protection circuit whitch can meet needs for both 2.7Gbps high speed and 2000V breakdown voltage.In the design requirements for high speed through the establishment of Hspice model, its simulation using Hspice, including the normal input signal as well as an example to 2000V Human Body Model simulation, the ideal high-speed aspects of the results obtained. As for breakdown voltage it is using the two-dimensional device simulation tool MEDICI to simulate from the perspective of the device, through the establishment and optimiztion of the device model,2000V breakdown voltage of human body model has been achieved.Above all,the ESD protection circuit design not only achieve 2.7Gbps high-speed requirements, but also meets the requirement of 2000V breakdown voltage.更多还原