基于FPGA的AFDX端系统设计

【作者】 罗西；

【导师】 胡小龙；

【作者基本信息】 中南大学 ， 计算机科学与技术， 2011， 硕士

【摘要】 AFDX是新一代飞机采用的航空电子信息传送系统。本文基于AFDX标准,搭建了一个基于FPGA的AFDX端系统开发平台。为简化硬件设计,AFDX端系统开发平台采用以Xilinx Virtex-4 FX12 FPGA为核心的SOPC。该FPGA包含了一个PowerPC 405处理器硬核和两个全双工以太网MAC硬核。PowerPC 405完成片内计算功能,双MAC实现AFDX冗余互联。航电接口方面采用CPCI接口与航电子系统实现互联。考虑到实现的方便性和灵活性,实现AFDX协议时,将AFDX特有的链路层和其他层分离。AFDX链路层部分采用自行设计的软IP核方式实现,完成接收过程中完整性检查、冗余管理,以及发送过程中流量调整、冗余管理等功能。考虑到端系统会根据实际需要采用不同调度算法,为便于将本IP核复用到其他设计方案,采用调度模块与IP核分离的设计。调度器由软件实现,调度算法在加权公平队列算法的基础上加入对帧发送时间的考虑,兼顾优先级、长度、帧间间隔、抖动多方面要求,对发送顺序进行调度。更多还原

【Abstract】 AFDX is the information transmitting system of the new generation airplane. The thesis builds a AFDX standard compatible AFDX end system developing platform, which bases on FPGA,To simplify the hardware design, The AFDX end system developing platform uses SOPC, which has a Xilinx Virtex-4 FX12 FPGA as its core. The FPGA embeds a PowerPC 405 and two MACs hardcores. The PowerPC 405 completes in-die computation. Two MACs connect with redundancy AFDX interconnection. CPCI interface is chosen to connect with avionics subsystem.Considering conveniences and flexibility, while complete AFDX protocol, the AFDX specific link layer is divided from other parts. The link layer is implemented by a soft IP core, including integrity checking, redundancy management in receiving processing and traffic regulation, redundancy management in transmitting processing.Considering different end system may use different scheduling algorithm, scheduling module is divided from IP core and implemented by software. Scheduling algorithm is based on weighted fair queuing, adds the consideration of frame transmitting time, overall consideration priority, length, BAG, jitter, schedules the sequence of transmitting.更多还原