【作者】 刘炎炎；

【导师】 欧阳一鸣；

【作者基本信息】 合肥工业大学 ， 计算机系统结构， 2011， 硕士

【摘要】 随着微电子技术的发展,超大规模集成电路的集成度越来越高,基于片上总线的SoC(System-on-a-Chip)在设计上遇到了全局时钟难以同步、地址空间有限、无法支持多节点并行通讯与系统扩展不够灵活等问题,严重制约了集成在单一芯片上SoC的规模及系统性能。片上网络(Network-on-Chip,NoC)将计算机宏观网络技术移植到芯片设计中来,采用由虫孔交换的路由机制组成的通讯架构来代替传统的总线架构,实现处理单元(IP核)之间的互联通信,从体系结构上解决了SoC总线架构带来的问题。NoC具有良好的空间可扩展性,低传输功耗和低延迟的特点,并具备良好的并行通讯能力。论文的主要工作正是为了验证NoC通讯架构的有效性,本文基于2D-Mesh拓扑结构展开研究,重点介绍了基于FPGA(Filed Programmable Gate Array)的NoC通讯架构的设计与测试。论文的工作主要包括三个方面:( 1) NoC通讯架构总体设计、IP核的添加以及内部模块的设计,其中NoC通讯架构内部模块主要包括路由器模块和资源网络接口(Resource-Network-Interface,RNI)模块以及通讯链路;(2)FPGA的概念介绍,重点描述了FPGA开发软件QuartusⅡ的设计流程以及基于FPGA的NoC的设计方法;(3)利用相关的综合测试软件对NoC通讯架构的设计分别进行详细的测试与性能分析。为了实现NoC架构的实际应用,我们搭建了基于FPGA的一种简单的2D-Mesh NoC通讯架构平台,通过添加相应的IP核实现两个ROM核中的数据传输到加法器核中相加,然后将运算结果存储到RAM核中。在此基础上给出了NoC架构中所有模块的结构设计与验证过程、数据包格式定义、并对各模块进行了必要的面积综合、功耗分析以及时序约束与时序分析,最后确定能够将整个NoC架构下载到FPGA开发板中进行实际验证。更多还原

【Abstract】 With the development of the microelectronics technology, the integrity of very large scale integrated circuit is getting higher and higher. SoC has to be designed with global clock synchronization, limited address space, unparallel communicate- on among multiple nodes and inflexible extension enough which has restricted in the scale and performance capabilities seriously in a single chip. NoC has been put forward the idea of the computer network technology to migrate to chip design. The IP cores communicate with each other by the wormholes exchange routing mechanism which has replaced the traditional bus architecture. NoC can solve the problems posed by the bus architecture. Besides, NoC has good expansibility, low transmission power consumption, low latency and parallel communication ability.This thesis is mainly targeted on verifying the effectiveness of the communication structure on the NoC. This have studied topology structure based on 2D-Mesh and the design and test methods about communication architecture based on FPGA of NoC. This thesis mainly includes three aspects: (1) the communication architecture to design on the NoC, the IP cores to add and the internal module to design. The internal module of NoC mainly include router, resource-network-inter- face and interconnects. (2) we have introduced the concept of FPGA, the design of software QuartusⅡdevelopment process and the NoC based on FPGA.(3) we use the related comprehensive software to test and verify the communication architecture and evaluate the performance of the NoC.In order to realize the practical application on the NoC, It have built a communication structure terrace of 2D-Mesh based on FPGA. We have accomplish- ed the data transferred and added in two ROM and saved the result into RAM by adding two IP cores. It have given the structural design, the verification process and the packet format defined about all modules on the NoC. Further more, This have given the area of the necessary comprehensive of all modules, power analysis, timing constraints and time-series analysis. It can verify the NoC architecture by downloading all to FPGA developing board.更多还原