【作者】 姜升；

【导师】 吴为民；

【作者基本信息】 北京交通大学 ， 计算机科学与技术， 2011， 硕士

【摘要】 多年来,集成电路测试是制约我国集成电路工业的“瓶颈”。在半导体技术工艺跨入深亚微米甚至纳米时代的今天,仅仅基于固定型故障的测试已经不再满足测试与可靠性的要求。对时延故障进行有效测试,已经成为生产测试的核心环节和集成电路测试领域的热点问题。本文基于布尔可满足性(SAT-based)从以下几个方面对通路时延故障的自动向量测试生成技术进行了研究,包括非鲁棒性测试,鲁棒性测试和跳变通路时延故障(transition path delay fault)测试,并提出了一种基于布尔可满足性的方法求解跳变通路时延故障模型下的测试问题。一、研究了通路时延故障模型的测试生成算法。通过七值逻辑系统及其编码,将电路中的逻辑蕴含关系以合取范式(CNF)的形式表示出来,以达到将ATPG问题公式化为可满足性问题的目的。在电路公式化的基础上,添加相应的通路敏化条件形成最终的合取范式,并使用SAT求解器来求解。这种方式比传统方法更加方便,效率更高。二、对跳变通路时延故障模型进行了研究。该模型是I. Pomeranz在2008年提出的新故障模型,本文对其进行了详细研究和分析,并且将之与通路时延故障模型进行了对比。这种模型是将通路时延故障模型和跳变时延故障模型结合起来的故障模型,主要用于测试通路子路径上小时延的积累所引起的跳变故障(transition faults)。跳变通路时延故障模型下的测试能够同时检测一条被测通路上的通路时延故障和所有的跳变故障。三、在跳变通路时延故障模型下,提出了一种基于布尔可满足性的测试生成算法。该算法借鉴了非鲁棒性测试生成算法,增加了部份约束条件。使用该算法对ISCAS’85基准电路进行测试,其结果显示了该算法的有效性。更多还原

【Abstract】 With the growing size and increasing complexity of VLSI circuits, the test generation for integrated circuit(IC) has been the bottleneck of IC industry of our country for years. The requirement of reliability can not be satisfied only by tests for stuck-at faults today, resulting in that Automatic test pattern generation (ATPG) for delay faults is becoming more and more significant.In this paper, ATPG problems for path delay faults are researched based on Boolean satisfiability (SAT), including non-robust tests, robust tests and transition path delay fault model. Meanwhile, the corresponding algorithms are presented and implemented. The contents of this paper are outlined as follow.1. Algorithms for test generation for path delay fault model are presented first. We discuss how to convert an ATPG problem to a SAT formula where both non-robust and robust test are considered. Based on the formulation of a circuit, constrains for sensitization of the circuit according to non-robust or robust tests are added, and the structured CNF formula is solved by a SAT-solver. Compare to the traditional algorithms, this approach is more convenient and efficient.2. A new fault model:transition path delay fault model presented by I. Promeranz in 2008, which is used for the detection of the faulty behavior caused by cumulated effects of small extra delays along a sub path, is analyzed in detail and compared with the path delay fault model in this paper. A test for a transition path delay fault satisfies the additional requirement that it detects all the transition faults along the path.3. An SAT-based algorithm for the test generation for transition path delay faults is proposed and compared with the path delay faults. Compared to an arbitrary non-robust test, a test for a transition path delay fault satisfies the additional requirement that it detects all the transition faults along the path. As a result, both the path delay fault and all the transition faults on the path are detected when an expected transition does not occur at the path output. The effectiveness of the algorithm is demonstrated on a set of ISCAS’85 benchmarks.更多还原