【作者】 周东；

【导师】 顾晓峰；

【作者基本信息】 江南大学 ， 微电子学与固体电子学， 2011， 硕士

【摘要】 应变硅技术通过采用适当的工艺或材料在MOS器件的沟道中引入应力,改变硅的能带结构、电导有效质量以及载流子的散射概率,提高载流子的迁移率。由于在提高器件电学性能方面的卓越表现,应变技术一直是半导体技术研究的焦点,并逐渐得到了应用。目前,业界对应变硅器件的研究主要集中在应力的引入方式、工艺改进及新型器件结构开发等方面。近年来,业界也开始越来越多地关注应变对MOS器件电学参数模型的影响,以及应变硅器件的稳定性、可靠性问题。例如,SiGe衬底应变MOS器件的阈值电压模型,应变MOS器件的关态漏电流、栅诱导泄漏电流(GIDL),偏压温度不稳定性(BTI)退化等。随着沟道应力的增加,在载流子迁移率提高的同时,应变MOS器件的高掺杂浓度、薄栅氧化层厚度、短沟道长度会引起泄漏电流的增大,使器件稳定性受到严重影响。本文首先针对SiGe源漏应变PMOS器件,在分析Si/SiGe的能带、态密度和本征载流子浓度等参数与Ge组分的基础上,通过求解一维及二维泊松方程,探索了影响SiGe源漏PMOS器件阈值电压的因素,并通过TCAD工具Sentaurus进行了验证。其次,利用变分法得到了SiGe源漏PMOS短沟道效应与SiGe源漏中Ge组分的关系,讨论了Ge组分对器件稳定性的影响。结果表明,应变PMOS的阈值电压随Ge组分的增加而减小,沟道长度及漏源电压也是影响应变PMOS阈值电压的关键因素,而Ge组分对器件短沟道效应的影响并不大。根据Intel公司90 nm工艺下栅长50 nm的PMOS单轴应变硅器件工艺流程,采用Sentaurus Process进行了工艺模拟,并依据已有测试结果对Sentaurus Device电学模拟结果进行了修正,对应变PMOS的关态漏电流、GIDL电流进行了模拟研究。结果表明,随着SiGe源漏Ge组分的增加,沟道应力增大,空穴迁移率提高,SiGe/Si之间价带差亦随之增大,引起关态漏电流增大;而GIDL电流随着Ge组分的增大而减小,且漏源电压较大时更易产生GIDL电流。最后,对严重影响深亚微米MOS器件寿命的BTI退化进行了研究。结果表明,相较于体Si器件,应变PMOS的NBTI退化更严重,温度的增加,以及氢在氧化层中扩散速率的增加均会增加NBTI的退化。更多还原

【Abstract】 Strained Si technology introduces stress to the channel of MOS devices by using appropriate process or materials. The band structure of Si, the conductivity effective mass and the carriers’scattering probability can be altered by stress, resulting in the favorable increase of carriers’mobility. Due to the good effeciency in improving the device performance, the strained Si technology has acquired focused research and successful applications in semiconductor industry. Current research efforts are more concentrated on the methods to introduce stress to the devices, process improvement, and developing novel device structures.Recently, wide attention has been paid to the effects of strain on electrical parameter models, as well as the stability and reliability of these novel devices, for example, the threshold voltage model of strained MOS with SiGe substrate, the off-state leakage current and the gate-induced drain leakage current (GIDL), the bias temperature instability (BTI). When the carriers’mobility increases with increasing channel stress, the high doping concentration, the thin gate oxide thickness and the short channel length of stained MOS devices may increase the leakage current, and deteriorate the stability of such devices.Based on the detailed analyses of Si/SiGe parameters, such as the band structure, density of states, intrinsic carrier concentration and Ge molar fraction, this thesis studies the factors influencing the threshold voltage of strained PMOS with SiGe source/drain (S/D) first by solving one-dimensional and two-dimensional Poisson’s equations. Results are also verified by the TCAD tool Sentaurus. Furthermore, the relation between the short channel effect and the Ge molar fraction is studied by solving the Poisson’s equation using the variation method. The effect of Ge molar fraction on the device stability is also discussed. Results indicate that the threshold voltage decreases with increasing Ge molar fraction. The channel length and the applied drain-source voltage of strained PMOS are also important influencing factors of the threshold voltage, while the Ge molar faction has a minor effect on the short channel effect.Moreover, the TCAD tool Sentaurus Process is applied to the process simulation of a uniaxial strained Si PMOS device with 50 nm gate length fabricated using Intel’s 90 nm processing technology. The original electrical simulation results from Sentaurus Device are calibrated according to the reported experimental data. The off-state leakage current and GIDL current are then studied by simulation. With increasing Ge molar fraction, the channel stress increases, resulting in the higher hole mobility and thus the larger valence band difference between SiGe and Si, and finally the increasing off-state leakage current. On the contrary, GIDL current decreases with increasing Ge molar fraction, and is easier to generate at higher applied drain-source voltage. Finally, the BTI degradation which has a severe effect on the life of deep sub-micron MOS devices is simulated. The results show that the NBTI degradation of strained PMOS is worse than that of bulk Si device. Increases of both the temperature and the diffusion rate of hydrogen in oxide can lead to severe NBTI degradation.更多还原