【作者】 赵寒秋；

【导师】 刘红侠； 于向红；

【作者基本信息】 西安电子科技大学 ， 软件工程， 2011， 硕士

【摘要】 在高速ADC中,高精度的时钟是整个芯片正常工作的保证,为了解决片外时钟的噪声、延时以及频率单一等问题,就需要在高速ADC中嵌入一个高精度的时钟发生器,来满足高速ADC对于时序的要求。基于锁相环的时钟发生器是一个可产生当今系统中所需的各种频率的低成本高效率方案,能够达到对于延迟和抖动等重要参数的更严格要求,但随着时钟频率的提高,锁相环的设计难度不断加大,而且功耗问题也尤为突出,在高频情况下更是如此。因此对于时钟发生器来说,提出新的设计方案就很有实用价值。本课题就是针对这一问题,综合考虑延时、功耗、面积等各种重要因素,设计了一种适用于500M Hz pipleline ADC的时钟发生器。本次设计采用TSMC 0.18 m m工艺实现,在延迟锁相环的基础上进行了重新设计,降低了时钟发生器的设计难度和功耗,设计主要分为三个模块:时钟缓冲电路、时钟占空比调节电路和时钟分频电路。时钟缓冲器采用差分Bicmos结构实现,可以有效的对时钟信号进行放大,提高时钟信号的驱动能力;时钟占空比调节电路采用基于延迟锁相环的改进电路来实现,主要分为频率合成器、电荷泵检测电路、延迟电路和整形器,其功能是用来调节外部时钟的占空比,以达到ADC对于时钟精度的要求;时钟分频电路主要完成对时钟信号进行分频的功能。当时钟发生器开始工作时,来自外部的时钟信号,经过时钟发生器的处理后,得到稳定的占空比为50%的时钟信号,作为采样保持电路的控制信号和其他ADC模块的时钟同步信号。更多还原

【Abstract】 In high-speed ADC, the high-precision clock is the guarantee of the entire chip. in order to solve the proplems such as noise, delay, single frequency and so on, we have to embed a high-precision clock generator into the high-speed ADC to meet the timing requirements of the high-speed ADC. Nowadays, the clock generator based on PLL is such a proposal that can provide a variety of frequencies with lower cost and more efficient. It also can meet the requirements of the important parameters of delay and jitter. But with the increasing of clock frequency, the design of PLL is becoming more and more difficulty, and the consumption of power is particularly prominent, especially in high frequency. Therefore, It is practical to propose a new design of clock generator. To the question, the delay, power, area and other important factors are considered and a clock generator that is suitable for 500M Hz pipleline ADC is designed.The design is achieved by TSMC 0.18 m mprocess. It is based on the delay-locked loop and redesigned to reduce the difficulty and power. The design consists of three modules: the clock buffer circuit, the duty-cycle correction circuit and frequency divider circuit. The clock buffer circuit is realized by the bicmos structure, it can efficiently zoom in the signal of clock and increase the driver ability of the signal. The duty-cycle correction circuit is based on the DLL circuit.It can be mainly divided into frequency synthesizer, charge pump detection circuit, delay circuit and shaper. It is used to adjust the duty-cycle of the clock to meet the precision requirements of ADC. The frequency divider circuit mainly completes the function of dividing frequence. A stable 50% duty -cycle clock is produced after the external clock is processed by the clock generator, and then it works as the control signals in the sample and holding circuit or the synchronization signals of other modules.更多还原