【作者】 李儒；

【导师】 朱樟明；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2011， 硕士

【摘要】 高速高分辨率CMOS D/A转换器是软件无线电SOC芯片的最核心IP核之一,也是现代移动通信、宽带成像雷达和现代无线网络等系统的关键部件,具有非常重要的地位和作用。D/A转换器的速度和分辨率是决定移动通信和软件无线电等系统性能的核心技术指标,移动通信和软件无线电应用急需高速(大于500MHz)高分辨率(大于12位)D/A转换器。高速高分辨率CMOS D/A转换器技术是超大规模集成电路技术的重要前沿和关键难点,是制约现代无线通信、软件无线电和雷达系统的关键瓶颈器件,我国移动通信、雷达和无线网络系统的发展,急需开展高速高分辨率数据转换器关键技术的研究和芯片开发。本文基于SMIC 0.18μm 1P6M标准CMOS工艺,实现了一种16位高速分段电流舵数模转换器,其中采样时钟频率为1GHz。16位1GHz数模转换器采用6-5-5的分段结构,其中高6位和中5位为温度计编码,低5位为二进制编码。电流源采用共源共栅结构以提高其输出阻抗,并通过基准电流来获得精确的电流值;提出了低摆幅低交叉点电流开关驱动电路,有效抑制输出Glitch现象的发生;采用了电流源阵列熔丝型校准电路,保证了电流单元的匹配性。16位1GHz数模转换器采用双电源供电,数字电源1.8V,模拟电源3.3V,采用差分输出结构,满量程输出电流10mA,通过外接电阻50?的电阻转换成输出电压。基于Cadence Spectre仿真器,对设计的16位1GHz数模转换器电路进行仿真,仿真结果如下:建立时间为1.4ns;积分非线性误差为±1.1LSB,微分非线性误差为±0.6LSB;输入信号为1MHz的正弦波,采样时钟频率为1GHz时的SFDR为78.1dB,芯片总功耗为123.39mW,芯片核心面积约为1.6mm×1.4mm,能满足现代无线通信及软件无线电的要求。更多还原

【Abstract】 High-speed, high-resolution CMOS D/A converter, being the most important part of software radio SOC chip IP core is a key component of modern mobile communications, broadband imaging radar systems and modern wireless networks. It makes a very important positon and role on the domain above. The speed and the resolution of the D/A converter are the most important parameters to determine the performance of mobile communications and software radio systems. High-speed(more than 500MHz) and high-resolution(more than 12 bit) D/A converter is urgent needed in the domain above. It is the forefront and key difficulty of VLSI technology, is the restriction to the development of the domain above. The research and exploiture on high-speed and high-resolution D/A converter chip is urgent needed for the development of mobile communications, radar and wireless networks system.Based on SMIC 0.18μm 1P6M standard CMOS process, a 16 bit high-speed segmented current-steering D/A converter is design in this thesis. The sampling clock frequency is 1G Hz, the segmented structure is 6+5+5, while the 6 most significant bits and the 5 intermediate significant bits are thermometer decode, and the 5 least significant bits are binary-weighted decode. Reference current and cascode structure are used to get a precise and high-output resistance current source. A low swing and low cross current switch drive schematic is design to reduses the glitch. Providing metal fuse current source calibration schematic makes sure the current unit matching. Using duplicate supply, while digital supply is 1.8V and analog supply is 3.3V. This thesis use a differential output structure, full-scale output current is 10mA, and we can transfer it to output voltage with a 50? resister.Based on Cadence environment, using Spectre to make a simulation to the D/A converter design in this thesis, and the simulation results are that, a settling time of 1.4ns; INL about±1.1LSB, DNL of±0.6LSB; when the input signal is a sinusoid with 1M Hz, and the sampling clock frequency is 1G Hz, the SFDR is 78.1dB; the whole power consumption is 123.39mW; the core chip area is about 1.6mm×1.4mm, it can be used in modern mobile communications and software radio system.更多还原