【摘要】 现场可编程门阵列(FPGA)内部专用进位链资源可应用于时间数字转换(TDC)的高精度测量。各级专用进位链的延迟时间很小,一般量级为数十皮秒至一百多皮秒。基于FPGA实现TDC精密测量要解决的一个核心问题是如何精确标定各级进位链的延迟时间,码密度法是实现延迟时间标定行之有效的手段之一。基于EP2S60F1020C4芯片,通过向进位链输入基准时钟周期范围内大量的随机脉冲,经统计处理得到每一级进位链单元的延迟时间。测试表明,延迟时间测量的分辨率为42.6 ps。更多还原

【Abstract】 The dedicated carry chain resources inside the field-programmable gate array(FPGA) can be applied for the high-precision measurement of time-to-digital conversion(TDC). The delay time for dedicated carry chains at all levels is very tiny, typically ranging from a few tens of picoseconds to one hundred picoseconds. One of the key issues to be solved in FPGA based TDC precision measurement is how to calibrate the delay time in all stages of the carry chain accurately. The code density method is one of the most effective ways to implement the delay time calibration. Based on the EP2S60F1020C4 chip, a large number of random pulses within a certain period of time are input into the carry chain, and the delay time at each level of carry chain unit is obtained by statistical processing. Tests have shown that the resolution of the delay time measurement is 42.6 ps.更多还原