【摘要】 在分析了嵌入式误码测试仪的使用需求和设计原理后,提出了一种基于FPGA的嵌入式误码测试仪的实现方法。通过对该实现方法的同步性能、误码计算方式进行分析、仿真,证明本方法具有可靠的同步特性,同时能够保证误码计算的实时性和连续性。嵌入式误码仪的实现使终端本身具有了误码测试功能,便于终端的自检测试及辅助系统故障定位。更多还原

【Abstract】 After analyzing the requirements and design theory of embedded bit error ratio tester (BERT), a method of embedded BER tester based on FPGA is put forward. The analysis and simulation results show that this method has reliable synchronization performance and can ensure real-time and continuous calculation of bit error ratio. The realization of embedded BERT makes a terminal have the function of bit error ratio testing, which can be convenient for self-testing of the terminal and fault location of the auxiliary system.更多还原