【作者】 安鹏；

【导师】 邵贝贝； 张健；

【作者基本信息】 清华大学 ， 核科学与技术， 2009， 博士

【摘要】 现今的数字计算系统已经渗透到社会的各个领域,可信计算系统的开发和研究将成为今后数字计算系统发展的主要趋势。在实现可信计算的各种途径中,论文将重点放在了对冗余技术的研究上。在对可信性理论和国内外现有的可信性实际系统进行调研后,经过各种冗余结构的比较,最终选定四重化冗余结构。针对四重化冗余结构热备切换输出端在实时性上的缺失,论文创新性地提出了四重化冗余竞争结构,在不减少原有结构性能的基础上,将两系同时晋升为工作系,输出端使用竞争输出的方式弥补这一缺失,实现切换时间的完全消除。在对四重化冗余竞争结构的可信性分析中,改进为原有分析方式对判别器和表决器模型建立的不足,使用瞬态失效和独立时间片累积求和的方法,计算及分析结果更加贴近实际系统。为验证理论分析,使用Matlab等仿真程序对可靠性结果进行仿真,与理论预期一致。在上述理论支持下,论文设计并实现了一套高可信性的计算平台。这一平台的构架即采用四重化冗余竞争结构,计算模块使用可信性指标非常高的PowerPC系列处理器,并使用FPGA作为判别器和竞争输出单元的硬件载体。外部总线使用标准的MIL-STD-1553B总线,整体硬件板卡采用6U欧式标准结构,双DIN41612标准针孔插接,可作为组件插入到背板中与其他组件协同工作。判别器内部的系统级软件采用Altera公司推出的嵌入式软核NiosII,两套判别器在FPGA内部构成双核系统。输出端使用竞争输出模块实现无缝切换,并采用强制指定输出系的方式对竞争冒险的极端情况做出有效的屏蔽。计算模块内部的系统级软件配套地移植μC/OS-II作为平台使用的操作系统。所有的底层软件均进行模块化设计,完善软件构架,最终应用层软件只需调用系统级软件的模块库即可。经实验验证,整个计算平台的可信性与实时性良好,适用于各种对可靠性和安全性要求很高的计算环境。更多还原

【Abstract】 Nowadays, digital computing systems have penetrated into all fields of society.The development and research Dependability Computing system will become the maintrends of the future development of digital computing systems.On the various ways of Dependability Computing systems for the realization, thethesis will focus on the research of redundancy technology. After the investigation onthe credibility of the theory and the existing domestic and international credibility ofthe actual system and redundance structure of various comparison, the QMR struc-ture is selected finally. The thesis put forward the innovative QMR of the competitionstructure based on the real-time missing. It can compensate this deficiency while noreducing the basis of performance. In the dependability analysis of the QMR compe-tition structure, taking into account the transient failure checker problem could makethe calculation and the results of the analysis closer to the actual system. To verify thetheoretical analysis, simulation program such as Matlab is adopted on the credibility ofthe results of simulation. The result is fully consistent with the theoretical expectations.In the theoretical support as above, the thesis designed and implemented a set ofhigh-dependability computing platform. The framework of this platform is QMR com-petition structure. Calculation module uses PowerPC Series processors with very highdependability performance. Judgement uses FPGA as hardware modules. Externalbus uses the standard MIL-STD-1553B bus protocol. The overall hardware board ac-cord with 6U continental standard structure and dual-DIN41612 standard plug, it canbe used as components inserted into the backplane with the other components worktogether. The system-level software in judgement chooses Altera Company’s embed-ded soft-core Nios II. There would be two sets of judgements in one FPGA internalconstitute dual-core system. In addition the use of competition in the output modulewill switch seamlessly. Calculation module within the system-level software supportto transplant the uC /OS-II as a platform to use operating system. All of the underlying software is designed as modular design and improve the software architecture. Theapplication-layer software could call the system-level software module library simply.After experimental verification, the entire computing platform has the advantageof dependability and real-time performance and could be applied to all kinds of relia-bility and security of demanding computing environments.更多还原