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高速集成电路互连的时域有限差分方法研究与性能优化

New Study Methodology of Finite-Difference Time-Domain and Performance Optimization for Interconnects in High Speed Integrated Circuits

【作者】 蒋乐乐

【导师】 毛军发;

【作者基本信息】 上海交通大学 , 电磁场与微波技术, 2008, 博士

【摘要】 随着高频高速集成电路(VLSI)的快速发展,电路中的电磁场效应越来越明显,为了能够正确模拟出在电磁场效应的影响下,高频电路系统信号的完整性问题,因而需要对电路里的互连封装结构进行电磁特性分析与设计。同时,由于三维集成电路及微波MCM这些新型结构的出现,使得该类结构内的电磁场问题不可忽略,这也对电磁特性仿真技术提出了新的要求。这些实际工程中出现的需要解决的问题均为计算电磁学的发展提供了强大的动力。作为计算电磁学中一类最为重要的方法,时域有限差分方法(FDTD)以其能够直接进行时域计算,适用范围广,实现手段简单,且通过一次时频变换就可以得到宽频带范围的信息等特点几乎被运用到电磁场领域中的各个方面。虽然时域有限差分方法的优点很明显,但该方法很大程度上会受到数值色散性和Courant-Friedrich-Levy(CFL)稳定性条件的约束。针对传统FDTD方法数值色散高的缺点,本文提出了一种可以构造高阶时域差分算法从而减少色散情况的辛时域有限差分方法(SFDTD)。SFDTD方法的原理来自于经典力学里Hamilton系统的辛算法,它是一种可保持Hamilton系统辛结构不变的显示时域差分方法。由于Maxwell方程本质上就是Hamilton系统的正则方程,因此用辛算法构造的高阶SFDTD方法具有高精度且非耗散的特点。本文全面分析了新的SFDTD方法的稳定性和色散性,结果显示出,传统的FDTD格式就等同于低阶的SFDTD方法,而高阶SFDTD方法与其相比则具有更低的各向异性和更小的相位误差。最后的数值实例证明了由于高阶SFDTD方法具有低的色散性,因而可以较显著地节省内存空间。针对传统FDTD方法有条件稳定的缺点,本文研究了一种基于精细积分的三维时域有限差分方法(PITD)。在以往提出的能够克服传统FDTD方法稳定性条件的技术中,交替方向隐式技术(ADI-FDTD)是最主要的一种方法。尽管ADI-FDTD方法能成功地消除稳定限制,但它的数值色散性会随着时间步长的增加而急剧恶化。而本文通过对PITD方法的稳定性条件和数值色散方程的推导,发现PITD方法可以采用远大于传统FDTD方法中受最大稳定限制的时间步长从而拓宽稳定性条件,并具有比ADI-FDTD方法更好的精度。PITD方法的数值色散误差可以被人为地控制而几乎与时间步长无关。但PITD方法的缺点是必须涉及大型矩阵方程的运算,其矩阵的维数是由空间网格数直接决定,因此该方法会占用大量的内存。本文也提出横向二维技术与精细积分方法相结合形成横向2-D PITD方法,使得在求解导波结构问题时可以缓解三维方法对内存的要求及避免对大型矩阵求逆的计算。除去对电磁学中计算新方法的研究外,本文也以电路分析的方式对片上全局互连线进行设计和优化。这是因为高速集成电路的发展使得片上全局互连线成为制约整个片上系统性能的瓶颈。集成电路设计也从以晶体管为中心的设计方案转变为以互连线为中心的设计方案。本文从互连线系统性能的各个方面入手,深入分析设计变量对这些性能的影响,并对性能各方面进行权衡折衷,以达到全局互连线系统的综合性能最优化。本文首先以分布式RC模型近似模拟插有多个缓冲器的一般结构的全局互连线,在分析线宽和线间距对RC时延、功耗、带宽等性能的影响后,提出时延-功耗-倒数带宽乘积最小化的优化目标,用以计算不同ITRS技术下最优的全局线宽和线间距,并评估了这种优化在各性能指标上产生的效果。随后本文以分布式RLC模型近似模拟插有多个缓冲器的双边屏蔽结构的全局互连线,在假定信号线与屏蔽线完全相同的情况下,分别分析了信号线宽度、信号线与地线间的间隔对RLC时延、功耗、带宽等性能的影响,提出了倒数时延-带宽乘积最大化的优化目标,用以计算不同ITRS技术下双边屏蔽结构最优的线宽和线间距,并评估了这种优化在各性能指标上产生的效果。本文最后研究了考虑热效应时的RC全局互连线横向尺寸的优化问题。在给出衬底温度模型、连线自热温度模型以及依靠温度的互连线和器件参数模型后,计算了作为顶层全局线宽度和间距函数的芯片温度并分析了线尺寸对温度的影响,以及线尺寸和温度对性能参数的影响。依然定义时延-功耗-倒数带宽积的折衷策略来优化计算不同ITRS技术下的线宽和线间距,并评估了这种优化在衬底和顶层连线温度及各性能指标上产生的效果。

【Abstract】 With the rapid development of high-frequency high-speed very large simulated integration (VLSI) circuits, the electromagnetic effects in VLSI circuits are more and more obvious. To resolve accurately the signal integration problems of high-frequency circuit systems under the impacts of electromagnetic effects, the analysis and design for electromagnetic characteristics of interconnect and package structures in circuits are necessary. Moreover, the appearances of new structures of three-dimension integrate circuits and microwave MCM make electromagnetics problems in these structures not be neglected, which also casues the new requirements for electromagnetic simulation software being proposed. The problems rising in the real engineering offer great power to the development of computational electromagnetics (CEM). As one of the most important methods in CEM, the finite-difference time-domain (FDTD) method has been applied to every aspect in electromagnetic fields since it can implement time-domain computation directly, and it can be applied in very broad areas with relatively simple realized techniques, and one single run of simulation can provide information over a large bandwidth. The advantages of the traditional FDTD method (Yee’s method) are apparent, however, the efficiency of the FDTD method is limited by the Courant-Friedrich-Levy (CFL) stability condition and numerical dispersion.To reduce the high dispersion error of the FDTD method,this dissertation proposes a high-order symplectic finite-difference time-domain (SFDTD) method. This method is a simple explicit integration time method which was originally developed to solve numerical systems derived from a Hamiltonian formulation and can preserve the symplectic structure of the systems constant. Maxwell equations can be treated as a Hamiltonian system, therefore, the SFDTD method based on symplectic integration technique is high accurate and nondissipative. The analysis of stability and dispersion of SFDTD method is roundly given. The resules show that the Yee’s method is equivalent to the low order SFDTD schemes, and hence the high order schemes have lower dispersion and smaller phase error compared to Yee’s method. The final numerical examples show that the high order SFDTD method can save greatly memory thanks to low dispersion.To remove the CFL stability condition of the FDTD method, this dissertation introduces a three-dimension finite-difference time-domain algorithm based on precise integration technique (PITD), too. Among all of the methods which have been proposed in the past to overcome the stability condition of traditional FDTD method, the ADI-FDTD method is the most improtant. It can eliminate the CFL limit successfully. However, in this method, the use of a large time step also increases greatly the dispersion errors. While in this dissertation, through discussing in detail the stability condition and numerical dispersion of PITD method, we discover that a larger time step than the maximum CFL limit of Yee’s scheme can be adopted and the better accuracy than ADI-FDTD method can be obtained by the PITD method. The dispersion error of PITD can be made nearly independent of the time step increment. However, this method involves the computation for large matrix equations and hence requires a number of memory spaces. This dissertation also subjusts to apply the compact two-dimension technique to the PITD method to develop a new compact 2-D PITD method, which can lighten a certain extent the requirement for memory of 3-D method and avoid the computation of invertible matrix for guided wave problems.Besides the study for the new approaches in CEM, this dissertation put efforts on global interconnect design and optimization with circuit analysis method. This is because that with technology scaling, global interconnects have started to limit the overall performance of a system-on-a-chip. The transistor-centric design has been turn to the interconnect-centric design in a VLSI circuit. In this dissertation, our goal is to attain the optimization of comprehensive performances of global interconnect system by means of the best tradeoff in all performances. We firstly consider distributed RC global interconnects with repeater insertion. After analyzing deeply the impacts of the line width and spacing on interconnect RC delay, power dissipation, bandwidth and total repeater area, a user-specified figure of merit which is a delay-power-reciprocal bandwidth tradeoff formulation is proposed to calculate the optimum width and spacing of global interconnects for various ITRS techniques nodes. This methodology is also used to quantify the effect of such optimization on every performance for various technology nodes.Next this dissertation considers the double-sided shielded global interconnect structure with repeater insertion using distributed RLC models. Assuming the same size and material are adopted in the signal line and shielded line, the effects of signal line width and spacing between the signal and shielded lines on the interconnect RLC delay, power dissipation, and bandwidth et al are analyzed all the round. A user-specified figure of merit which is a bandwidth-reciprocal delay tradeoff formulation is then proposed to calculate the optimum width and spacing of double-sided shielded interconnects for various ITRS technique nodes, and the effect of such optimization on every performance is also quantified.This dissertation finally introduces the analysis and optimization problem of thermal-driven global interconnects. After the thermal models and temperature-dependent interconnect and device models are present respectively, we compute the temperature as the function of topmost global interconnect width and spacing and analyze the impacts of interconnect size on global interconnect temperature and substrate temperature, and the size as well as temperature on interconnect performances. The same figure of merit that a delay-power-reciprocal bandwidth product is defined to optimize interconnect width and spacing and quantify the effect of such optimization on interconnect performances and topmost interconnect and substrate temperature for various ITRS technique nodes.

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