【作者】 姚睿；

【导师】 于盛林；

【作者基本信息】 南京航空航天大学 ， 测试计量技术及仪器， 2008， 博士

【摘要】 进化硬件是一种将进化算法与可重构器件有机结合的硬件系统,它与传统硬件的不同在于其具有自组织、自适应和自修复能力。进化硬件的研究对新型智能电路和芯片设计方法,对构建自组织、自适应和自修复的硬件系统,对解决当前复杂集成电路和芯片设计中面临的各种重大问题,对实现航空航天飞行器的高可靠性、长期可用性,都具有非常重要的理论意义和实用价值。针对数字进化硬件的关键技术,论文分别研究了进化算法的设计与应用、复杂数字电路的在线进化技术及基于进化硬件的强容错三模冗余系统结构与容错机制。1.给出了进化算法模型与设计步骤,对其4个分支进行了分析与比较,提出了一种基于进化算法的自适应形态滤波器结构及设计方法,以遗传算法作为优化工具,在Xilinx XCV2000-E FPGA上对滤波器结构和参数(滤波算法、结构元素形状和尺寸)进行在线优化。对典型噪声的滤波结果表明,该滤波器能够根据噪声的不同自适应调整结构和参数,鲁棒性好,滤波性能优于均值滤波器和中值滤波器,且该滤波器采用硬件实现,便于在嵌入式系统中应用。2.为提高进化收敛速度,提出了一种基于猴王婚配机制的免疫遗传算法,模拟猴王婚配机制将交叉有效引至算法中,并保留最优个体以保证算法的收敛性,同时通过双变异、自适应变异和模拟褪火等机制提高搜索效率,采用相异矩阵和模糊选择法简化计算过程。给出了算法原理、步骤和收敛性证明,通过函数优化、数字逻辑电路在线进化和图像滤波器的在线进化对算法性能进行了测试,结果表明,该算法可有效克服遗传算法的早熟收敛问题,加快收敛速度。3.分析了进化大规模电路存在的困难和解决方法,针对寄存器级数字电路的进化,提出了生长进化方法。该方法首先将复杂电路分解为不同的种子电路,然后结合L系统的生长方法递增进化,随时保护已进化成功的电路结构,并采用增长验证评估方法解决在线验证评估难题。结果表明,采用生长进化方法进化出的电路规模和进化速度均优于传统的直接进化方法。4.针对片上系统进化,提出了一种基于可进化实时可参数化核(RTP核)的设计方法,可根据用户设计实时改变软IP核的功能。给出了可进化RTP核的概念和模型,并以HDB3编码器设计为例,给出了可进化RTP核的进化设计方法和基于可进化RTP核的片上系统设计方法。使用可进化RTP核可实现片上系统的在线进化、自适应与自修复,为进化硬件的工程应用提供了一种可行的实现方法。5.为提高太空恶劣环境中电子系统的可靠性,将进化硬件与传统三模冗余(TMR)容错思想相结合,提出了一种具有多种在线自修复机制的强容错TMR系统结构及设计方法,可以在不影响系统正常工作的前提下实现故障模块的在线修复。该系统采用TMR结构,可实时检测并定位故障模块;模块中每个组件均有备件,故障发生时可通过备件切换法快速自修复,同时模块中每个组件也可通过进化进行修复;另外还通过异构冗余设计降低2个以上模块同时发生故障的概率。给出了系统结构和可靠性模型,推出了可靠性计算公式,对系统的可靠性进行了理论分析,并以具有片内三模冗余的HDB3编码器系统设计为例进行验证,结果表明系统可靠性得到很大提高。更多还原

【Abstract】 Evolvable hardware is a kind of hardware system that integrates the evolutionary algorithm with the reconfigurable hardware organically. And the capabilities of self-organization, self-adaption and self-repair make it much larruping from the conventional hardware. There are great value of practicality and theoretical meaning to research on evolvable hardware, for the design of the new smart circuits and CMOS chips, for the construction of self-organizing, self-adaptive and self-repairing hardware systems, for the open problems of designing complex integrate circuits and CMOS chips, and for the requirement of high reliability and long mission life of the space aircrafts.In this thesis, key technologies of digital evolvable hardware, including the design and applications of evolutionary algorithm, the online evolution technologies of the complex digital circuits, and the system structure and fault-tolerance mechanisms of the evolvable hardware-based triple-module redundancy systems, have been explored.1. The model and design steps of evolutionary algorithm is given, and analysis and comparison is given on its four main branches. A system structure and design method of adaptive mathematical morphology filter based on evolutionary algorithm is proposed. Not only filtering algorithms can be adjusted adaptively, but also shape, amplitude and width of the structure elements can be regulated automatically. Taking genetic algorithm as optimizing engine, the architecture of filter is implemented on Xilinx XCV2000-E FPGA and optimized online. Results of online filtering show that the filter can adjust its architecture and parameters adaptively according to different types of noises, thus has good robustness and better filtering performance than mean filter and median filter. Moreover, the filter is implemented on hardware, which makes it a very promising filter for embedded systems.2. An immune genetic algorithm based on the monkey-king’s marriage mechanism (MMIGA) is proposed to accelerate the convergence speed. The antibody set is modeled as a monkey colony, which is divided into male and female sub-colonies according to the individual’s affinity to the antigen, and the super individual is the monkey-king. All the female monkeys marry to the monkey-king with a certain probability and then perform gene mutation to breed descendants; the male monkeys breed descendants by simulating the immune response process of cloning, adaptive mutating, annealing keeping and fuzzy dislike matrix selecting; whereas the monkey-king is maintained to the next generation. The principles, steps and convergence proof of MMIGA are given. Contrast studies in function optimization, online evolutionary design of digital circuits and image filter indicate the superior performance of MMIGA over the genetic algorithm.3. The difficulties and probable solutions on evolving complerx digital circuits are analyzed, and aiming at the difficulty of evolving complex circuits, a growing evolutionary approach suitable for online evolution is proposed. The complex digital circuit is decomposed into simpler seed circuits, then the evolution approach that simulates the process of the plant’s growth unties the circuits’scalability. Meanwhile, in order to solve the online evaluation problem, an incremental evaluation approach is used to substitute for the conventional exhaustive evaluation method, which enhanced the evolution speed greatly. Contrast results show that the growing approach performs more effective than evolving directly, whether on the electric circuits’scale or the evolution speed.4. Aiming at evolving systems-on-chip, a new online design method is proposed, in which the run-time parameterizable (RTP) cores are utilized as building blocks, and the function of the soft IP core may change real time according to consumer’s demand. The concept and model of evolvable RTP core is given, and the design method is proof-tested by a HDB3 coder system-on-chip. Using the building blocks of evolvable RTP cores, digital hardware systems can be evolutionary designed online, and perform self-adapting and self-repairing online, thus open a viable way for the real-world applications of evolvable hardware.5. A new system structure and design method of triple-module redundancy (TMR) systems with multi-ply online self-repair mechanisms that need not affect the system’s normal operation is proposed by introducing evolvable hardware into the traditional TMR system. The system has a structure of TMR in the mass, which can check the fault module autonomously; each module is made up of subassemblies with spare parts, and can recover from fault quickly by switching to the spare parts; while each subassembly in the module can be repaired through evolution; moreover, redundant circuits with different structures are applied to avoid the synchronously arriving of fault at more than 2 modules. The system structure and reliability model is given, the reliability formula is educed, and the reliability of the system is analyzed in theory. The design method is proof-tested by a TMR HDB3 coder system-on-chip. It is shown that the reliability of the system has been enhanced greatly.更多还原