【作者】 俞洋；

【导师】 彭喜元；

【作者基本信息】 哈尔滨工业大学 ， 仪器科学与技术， 2008， 博士

【摘要】 随着集成电路工艺技术和设计方法的提高,集成电路的规模越来越大,使得原来要由多个芯片才可以实现的复杂系统被集成在单个芯片上成为可能。在这种背景下,系统芯片(SOC, System-on-a-Chip)应运而生。SOC技术采用IP核复用的设计方法,将整个系统映射到单个芯片上,既可以加快开发进度,又可以缩小产品体积、提高系统性能,近年来得到了广泛的应用。然而随着SOC集成的IP核数目的增多,其功能越来越复杂,SOC的测试数据量、测试功耗也随之急剧增加,对各个IP核进行测试访问也变得更加困难,这些都为SOC测试带来更大的挑战。本文在研究SOC测试结构的基础上,对当前SOC测试中存在的问题进行分析,重点针对测试数据量大、测试功耗高和测试时间长这三个关键问题进行研究,提出了相应的解决方法,并在ISCAS’89和ITC’02标准测试集上进行仿真实验,验证了方法的有效性和实用价值。本文的主要研究内容和成果如下:1.对基于编码的测试压缩方法进行研究,针对测试数据预处理中差分操作后测试集中数据“1”的比例较高的问题,提出了基于蚁群算法的测试向量排序算法,以进一步提高压缩效率;针对目前大多数编码压缩方法仅针对测试数据中的0游程进行压缩的现状,提出了一种同时考虑0游程与1游程的变游程编码方法,该方法在应用中不需要对原始数据作差分变换,因此能在提高压缩效率的同时减少解码的硬件开销;2.研究适用于多扫描链IP核的测试数据压缩方法,在分析字典方法基本原理的基础上,对其进行改进,提出了压缩比更高的基于频率指示索引字典的多扫描链测试数据压缩算法;本文利用测试数据间的重复性,提出了基于子向量重复性的测试数据压缩算法;仿真实验表明,两种多扫描链测试压缩算法都能够取得较高的压缩效率;3.在分析测试功耗产生原因的基础上,本文提出了基于扫描链冻结的测试功耗优化方法,以降低扫描测试中触发器的无用跳变次数,进而降低扫描测试功耗;4.针对IP核串行测试封装结构造成测试功耗过高的问题,利用测试向量中的完全重叠和部分重叠现象,本文提出基于部分重叠向量的并行测试封装结构,以解决串行封装结构测试功耗过高的问题,仿真实验证明了该方法的有效性;5.在研究测试访问机制(TAM, Test Access Mechanism)结构的基础上,讨论TAM结构优化与测试调度问题,提出了基于Two-Stage GA的测试调度算法,该方法采用灵活的测试总线分配方案,使得SOC系统级测试时间得到进一步降低。更多还原

【Abstract】 With the continuous improvements in the semiconductor manufacturing technology, the integrated circuits is becoming more and more complex, and tens or even hundreds of millions of transistors can be integrated into a silicon die, which promotes the advent of System-On-a-Chip (SOC). The design of SOC mainly adopts the technique of reusable Intellectual-Property (IP) cores, and maps the whole system to a single chip, so it can shorten the time to market, and lower the cost of chips. SOC can greatly reduce the size of products and improve the performance of the system by reducing the delay between chips. Therefore, it has been widely used in many industrial fields in recent years.However, with the increase of the number of IP cores integrated in SOC, the functions of SOC are becoming more complex. Therefore, SOC test data volume and test power consumption grow rapidly, and test access is also more difficult. All these cases bring more challenges to SOC test.Based on the SOC test architecture, the problems exist in SOC testing domain are discussed. This dissertation aims at solving the problems of huge test data, high power dissipation and long test time appearing in SOC testing, and makes research in test compression, test power optimization and test scheduling.The main contents and research contributions of this dissertation are as follows:1. Test compression methods based on coding are firstly discussed. In order to reduce the percentage of“1”in the test set after difference operation, a test vector reorder algorithm based on ACO optimization is proposed. At present, most test compression methods based on coding adopt the idea of dealing with runs of 0’s. A test compression approach based on Variable-Run-Length code is proposed in this dissertation. Both runs of 0’s and runs of 1’s in test data stream are mapped to codeword so as to reduce the number of short runs and improve compression ratio.2. Test compression methods for multi-scan chains are studied. A novel test compression method using dictionaries with frequency-directed indices (FDI) is proposed to reduce the test data volume in SOCs. In the meanwhile, considering repetition between test vectors, a test compression algorithm based on sub-vector repetition is also proposed. Experimental results show that the two methods are both effective in reducing test data volumes.3. Based on the possible reasons of high power dissipation, an efficient test power optimization algorithm based on scan chain frozen is proposed. This method reduces the switching activities so as to reduce scan test power.4. In order to decrease the test power consumption when using serial test wrapper, a parellel test wrapper architecture is proposed in this dissertation. The new wrapper makes use of the superposition among test vectors. Experimental results show the validity of the proposed method.5. TAM optimization and SOC test scheduling problem are studied in this dissertation. A test scheduling algorithm based on two-stage GA is proposed to co-optimized TAM partitioning and test scheduling. Experimental results show the proposed algorithm is effective in reducing SOC test time.更多还原