电阻型存储器器件与工艺研究

【作者】 吕杭炳；

【导师】 汤庭鳌； 林殷茵；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2008， 博士

【摘要】 存储器在半导体市场中占有重要的地位,随着便携式电子设备的不断普及,不挥发存储器在整个存储器市场中的份额也越来越大。目前,Flash占据了不挥发存储器市场90%的份额,但随着半导体工艺节点的不断推进,Flash遇到了越来越多的瓶颈问题,比如浮栅厚度不能随器件尺寸的减小而无限制减薄,有报道预测Flash技术的极限在32nm左右,此外,Flash的其他技术缺点也限制了它的应用,如写入速度慢,操作电压高等。这就迫使人们寻找性能更为优越的下一代不挥发存储器。最近电阻存储器因其高密度、低成本等特点受到了高度关注,所使用的材料有相变材料、掺杂的SrZrO₃、铁电材料PbZrTiO₃、铁磁材料Pr_1-xCa_xMnO₃、二元金属氧化物材料、有机材料等,受电或热等能量的作用下,在高阻和低阻态之间转换。以相变材料为存储介质的阻性存储器亦被称作为相变存储器（Phase Change Memroy,简称PCM）,在读写速度、读写次数、数据保持时间、单元面积、多值实现等诸多方面都具有极大的优越性,成为未来不挥发存储技术市场主流产品最有力的竞争者之一。目前应用最广泛的是GeSbTe（简称GST）合金材料,在电的作用下使其在晶态和非晶态之间转换,对应为器件的低阻态和高阻态。当前,在相变存储器研究领域中,写操作电流（RESET电流）过大是阻碍其商业化的一个关键问题,降低RESET电流主要从两方面考虑,对常用的GST材料进行掺杂改性或者开发新型相变材料;另一方面,减小器件尺寸和相变薄膜厚度,减小相变区域,从而降低发生转变时需要的能量,然而,传统器件的尺寸依赖于光刻技术。本论文第一部分主要围绕3D相变存储器器件设计展开,利用边墙定位技术,构建3D纳米相变存储器,其电极横截面积取决于电极材料的厚度和台阶高度,使器件尺寸完全突破光刻限制,不需要先进的光刻技术,极大的降低了生产成本,在大尺寸工艺下,依然可以获得纳米级器件尺寸。在5μm实验室工艺条件下成功获得了100nm以下纳米相变存储器阵列。以金属氧化物为介质的电阻型存储器通常被称为阻性存储器（ResistiveRandom Access Memory,简称RRAM）。其中,二元金属氧化物（如Nb₂O₅,Al₂O₃,Ta₂O₅,TixO,NixO,Cu_xO等）,因为其器件结构简单、成分精确可控而受到格外关注。Cu_xO（x＜2）作为两元金属氧化物中的一种,其优势更为明显,因为Cu在现在的半导体后端互联工艺中广泛应用,以Cu_xO为基的阻性存储器件可与互联工艺完美兼容而不需要引入新元素。本论文第二部分主要围绕Cu_xO基阻性存储器展开,用反应离子（RIE）氧化进行Cu_xO制备,对器件的forming电压、疲劳特性、保持特性进行了研究,提出了上电极界面处的局部导电通道的形成与关断的电阻转换模型,基于双大马士革工艺,提出相应的与铜互连后端工艺集成的解决方案,为生产低成本、高密度、高可靠性的Cu_xO电阻存储器奠定了基础。更多还原

【Abstract】 Memories play important roles in semiconductor market.With the population of mobile electrical device,the non-volatile memory is getting more and more important in the total memory market.Currently, Flash is dominant in memory area,with 90%market share.As the scaling of semiconductor technology,Flash memory encounters more and more bottlenecks,e.g.,the thickness of floating gate can not be decreased infinitely.According to some reports,the limitation of Flash technology would be at 32 nm node or so.Moreover,other shortcoming such as low programming speed,high operating voltage etc,also limit the application of Flash,which forces people to search more excellent technology for next generation non-volatile memory.Recently,resistance type memories are attracted great attention for their high density and low cost.Many materials with switching characteristics were discovered,e.g. chalcogenides,doped SrZrO₃,PbZrTiO₃,Pr_1-xCa_xMnO₃,binary metal oxide and organic materials.The resistance type memories based on chalcogenides are also called phase change memory（PCM）,which has great advantages on speed,endurance,retention,cell size and multi-level storage.It is one of the most promising candidates for next generation non-volatile memory. The most commonly used material in PCM is GeSbTe,which can transit between amorphous state and crystalline state,corresponding to high and low resistance state.Currently,the main problem preventing PCM from application is the large RESET current.There are mainly two ways to reduce the RESET current.One approach is doping in commonly used GST material or searching new phase change materials.The other one is reducing cell size.The first part of this thesis is mainly focused on design and fabrication of 3D nano device of phase change memory.By using spacer pattern technology,the cross-section area of electrode is defined by the height of step and film thickness,which is totally independent of lithographic technology.By using this method,sub-100 nm sized memory array are successfully fabricated with no need of advanced lithographic equipment.The manufacturing cost is greatly reduced.Metal oxides based resistance type memories are also called resistive switching memory（Resistive Random Access Memory,RRAM）.Binary metal oxide（such as Nb₂O₅,A1₂O₃,Ta₂O₅,Ti_xO,Ni_xO,Cu_xO,etc.）are attracted great attention,because of their simple structure and composition.Among them, Cu_xO has more advantages,because Cu is widely used in modern semiconductor manufacturing and the fabrication of a Cu_xO memory cell is perfectly compatible with standard Cu interconnect processes.The second part of this thesis is mainly focused on Cu_xO resistive switching memory.Take RIE method for Cu_xO preparation and investigate the critical characteristics of devices,such as forming voltage,endurance and retention,etc.And then raise a switching model of local conductive formation and rupture near the interface between Cu_xO and top electrode based on experiment data.Finally,the integration solution based on damascene Cu interconnect process is put forwards,which further lays foundation for producing high density,low cost and high reliable Cu_xO based RRAM.更多还原