UWB系统中时钟电路的研究与设计

【作者】 郑永正；

【导师】 洪志良；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2009， 博士

【摘要】 超宽带系统由于其本身的突出优点，具有广阔的应用前景。本论文以应用于多边带正交频分复用超宽带无线接收机的频率综合器为出发点，从几个方面对频率综合器进行了深入的研究。本论文首先回顾了超宽带无线通信系统的发展历史，对多边带正交频分复用超宽带系统做了基本的介绍，推导了该协议对于频率综合器的性能要求，对各种频率综合器体系结构的优缺点进行了分析和比较，并在此基础上确定了最适合的体系结构为双锁相环路结构。其次介绍了频率综合器系统中四阶锁相环路的系统设计，给出了锁相环路系统模型及系统参数设计流程，讨论了环路的稳定性与环路带宽的关系，给出了锁相环路的各模型噪声模型及总的输出相位噪声，并提出了一个应用在锁相环中的自适应频率校准电路的设计方法。接着对应用在分数分频锁相环中的ΣΔ调制器进行了较为深入的理论分析，内容包括了量化噪声分析，环路带宽要求，电荷泵电流失配对输出相位噪声的影响，以及减小ΣΔ调制器量化噪声的方法。这里给出的分析对电路设计者具有较强的指导作用。然后对锁相环路中最主要的电路模块，即压控振荡器的设计进行了各方面的分析和讨论。内容主要包括以下几个方面，即电路构成，性能参数，螺旋电感与可变电容，相位噪声模型，相位噪声优化技术，并给出了压控振荡器正交信号的产生方法。论文最后给出了一个应用于MB-OFDM超宽带系统中“模式一”3子带快速跳频频率综合器的设计，并采用0．13μm CMOS工艺进行流片，给出了芯片照片和测试结果，测试结果表明2．112GHz和3．96GHz两个锁相环输出参考频率杂散均小于-60dBc，在1MHz频偏处的点相位噪声均小于-110dBc／Hz，频率综合器输出带内杂散小于-50dBc，带外杂散小于-30dBc，而且其它各项输出测试性能均满足系统指标要求。在此基础上又给出了一个8子带快速跳频频率综合器的系统构架和电路实现。更多还原

【Abstract】 The ultra-wideband (UWB) system has expansive market applications due to itsoutstanding advantages.A deep research of monolithic CMOS frequency synthesizerfor MB-OFDM UWB receiver is presented in several aspects in this thesis.Firstly,a review of the history about UWB communication development is given.The fundamentals of MB-OFDM UWB system are introduced.The designspecifications of the frequency synthesizer are deduced.Based on the analysis andcomparison of different architectures,the dual-PLL architecture is selected to be themost approximate one.Secondly,system design of the fourth-order phase-locked loop is introduced.ThePLL system model and parameter design flow are given.The relationship of the loopstability and open loop bandwidth is discussed.Each individual noise model of thePLL building blocks and the overall phase noise at the PLL output are presented.Anadaptive frequency calibration (AFC) design method for PLL is proposed.Thirdly,the profound theoretical analysis of theΣΔmodulator for thefractional-N PLL is presented,which includes theΣΔquantization noise,therequirement of the PLL bandwidth,the impact of the charge pump current mismatchto phase noise,and the method of suppressing theΣΔquantization noise.The analysisgiven here has a strong guidance to the circuit designers.Fourthly,the design of the voltage-controlled oscillator,which is the mostimportant building block in PLL,is analyzed and discussed.The content incorporatesthe circuit architecture,performance parameters,spiral inductor and varactor,thephase noise model,and the phase noise optimizing technique.Then the quadraturesignal generation technique is given.Finally,the design of a fast hopping CMOS frequency synthesizer for“mode 1”MB-OFDM UWB system in 0.13μm CMOS process is presented.The die photographis given.The experimental results show that the reference sidebands of both PLLs(2.112GHz and 3.96GHz) are smaller than -60dBc.The spot phase noise is betterthan -ll0dBc/Hz on 1MHz frequency offset.The in-band spur is smaller than-30dBc and the out-of-band spur is smaller than -50dBc.Other measurementperformances also meet the design specifications.Then the system architecture andcircuit design of another fast hopping 8-band frequency synthesizer are presented.更多还原