超高频射频识别读写器芯片关键技术的研究与实现

【作者】 谈熙；

【导师】 闵昊；

【作者基本信息】 复旦大学 ， 微电子与固体电子学， 2008， 博士

【摘要】 超高频射频识别系统由于其适中的传输距离,较快的通信速率以及较小的天线尺寸而在近年来得到学术界和应用领域越来越多的关注。而其中无源标签系统由于标签的体积小,成本低而可以在大范围内应用,在物流,仓储,物品管理及追踪,防伪等领域具有广泛的应用前景。但是由于标签对功耗和成本的限制,系统对读写器的性能要求很高,因此目前市场上大部分的读写器是基于高性能分立器件(尤其是射频模块)搭建而成,这直接导致了读写器成本居高不下,阻碍了RFID系统大规模的推广和使用。目前读写器的单芯片化趋势已经越来越明显,将读写器的主要功能模块(收发机,数字基带处理)集成到一颗芯片中的方案除了可以有效地降低读写器成本以外,还可以大大减小读写器功耗和体积,对低功耗,低成本读写器的设计具有很大的吸引力。本论文研究了900MHz频段RFID读写器芯片在CMOS工艺下的实现,完成了从系统分析,建模,到系统架构设计,电路设计,硬件实现并最后通过测试验证的整个流程。在系统设计阶段,主要有以下创新点和成果:1.通过解析分析方法,确定了符号长度不一致的PIE编码数据的功率谱表达式,得到的理论结果与数值仿真结果一致,对系统设计具有指导意义;2.通过详细分析DSB-ASK,SSB-ASK及PR-ASK这3种调制方式以及标签返回的FM0及Miller编码信号的特征,确定了读写器发射信号在基带成型滤波之后的功率分布,以及标签反射调制信号的功率谱特征,给出了实际应用中信道带宽和数据率的合理取值。该分析结果在2006年10月提交至信产部无线电管理委员会频率规划处,做为制定超高频RFID中国频率规范的参考。该频率规范试行稿于2007年5月出台;在电路设计部分,读写器本地载波泄漏的处理是射频识别读写器设计的最大难点之一,为了使1.8V电源电压的CMOS接收机在收到0dBm以上的本地载波干扰同时,能够正常处理-70dBm至-40dBm的信号,采用了以下创新性设计:3.芯片中接收机采用了第一级为单平衡无源混频器的特殊结构,以提高电路的输入压缩点。由于无法使用低噪声放大器来抑制后级噪声,无源混频器的低闪烁噪声特性有效控制了接收机噪声系数。同时,单平衡结构可以提供单端到差分转换,可以省去对片外balun的需要;4.由于无源混频器的输出阻抗较高,后级无法使用常见的低输入阻抗并联输入反馈全差分运放结构进行直流消除,而需要首先经过一个高阻输入级做为缓冲。芯片中使用2级串联输入负反馈级联结构放大器,通过合理分配增益和噪声指标,同时实现了无源混频器输出缓冲,直流消除,和基带低噪声信号放大的功能。此外,由于载波泄漏下变频后产生的直流分量很大,设计中采用了基于轨对轨运放的伪差分结构,使得直流消除范围与传统全差分结构相比大大增加。该芯片在SMIC 0.18um mixed signal CMOS工艺上实现,芯片核心电压1.8V,数字I/O接口电压3.3V,整个芯片面积为3.2~*3.5mm~2,工作电流为140mA(不包括片上驱动放大器)。芯片测试结果显示,当载波泄漏为0dBm时,接收机中频放大器输出最大噪声为-70dBm/Hz,其主要成分是频率综合器相位噪声经过下变频及基带放大之后形成的。该测试结果给出了具有指导意义的结果:5.在直接变频结构的RFID接收机中,本地载波泄漏在下变频时,由于相位噪声的相关性,会导致一定程度的噪声抵消,在本设计中抵消的幅度测试为17dB左右。该结论对于后续工作中确定读写器中频综合器相位噪声指标具有很大的指导意义。为了验证收发机芯片的完整功能,完成了读写器原型机的设计,包括收发机芯片,数字接收机,基带协议处理,接口,电源管理及上位机等。测试结果显示,该原型机能够完成完整的读写器-标签通信。读写器通过PC中上位机的控制发出指令,并将接收到的标签返回数据处理后在终端上显示。测试中得到正常工作最远距离为30cm,此时读写器发射功率为20dBm。实验证明,此时由于载波泄漏中噪声占主导地位,增加发射功率时接收机噪声也随之增加,对读写器距离的改善并无帮助。因此,如何减小载波泄漏对接收机噪声性能的影响将是未来工作中的重点。更多还原

【Abstract】 Due to the moderate communication distance, data rate and antenna size, the ultra high frequency (UHF) band radio frequency identification (RFID) system is getting more attention in recent years in both industry and adaceme. Particularly, the passive tag benefiting from small size and less expensive is widly applicable in logistics, storage, asset management, tracking and tracing, anti-counterfeit, etc. But the power and cost limitation on passive tags requires high performance readers to guarantee the system functionality in various enviroments. So most of the commercial RFID readers now are based on high performance but also expensive discrete components (especially RF modules), that makes readers cost high and hinders the mass adoption of RFID system. The reader chip which integrates the main modules of reader (transceiver, base band processor) into a SOC chip can reduce the cost, power consumption and volume of reader greatly, makes the single chip architecture attractive, especially for low cost low power reader design.This thesis designed the reader chip for 900MHz band passive tag RFID system and implemented the chip on CMOS technology. System analysis, system modeling, architecture design, circuit design, implementation, testing and prototyping are included. In the system design phase, the main contributions and results are:1. By analytical analysis, the closed form solution of unequal symbol length PIE coding power spectrum density (PSD) is derived. The conclusion is consistent with simulation results, and is deducible in the system design;2. By a detailed analysis to the DSB-ASK, SSB-ASK, PR-ASK modulated signal, and FMO/Miller coded returning signal, the power distribution of transmitted signal after the baseband pulse shaping filtering, and the spectrum characteristics of backscattered signal is given. Accordingly, the recommended channel bandwidth and data rate is given and submitted to the state radio regulatory committee (SRRC) as the reference of UHF RFID regulation in China. The reference was accepted in Oct. 2006, and the draft of regulation was announced in May. 2007.The high power local carrier leakage is the most difficult part to be deal with in the circuit design. To process a signal at the level of -70dBm to -40dBm, coexisted with a OdBm local carrier leakage in a 1.8V CMOS receiver, the following new schemes are used:3. A single balanced passive mixer is used as the first stage of receiver, for its high input compression point and low flicker noise, where the latter is important at the absence of low noise amplifier (LNA). Besides, the single balanced structure can provide single-ended to differential conversion, so the off-chip balun can be eliminated;4. The high output impedance of passive mixer will reduce the performance of the conversional DC cancellation structure based on shunt-shunt feedback and full differential amplifier. Instead, buffer stage with high input impedance is needed following the passive mixer. In this design, a 2 stage structure with proper distribution of gain and noise, realizes the mixer buffering, DC cancelling and baseband low noise amplification. And pseudo differential structure based on rail-to-rail amplifier is adopted to accommodate the large DC component sourced from the down-converted carrier leakage.This chip is implemented using SMIC 0.18um mixed signal CMOS technology, the core voltage is 1.8V, digital I/O voltage is 3.3V, occupies 3.2~*3.5mm~2, current consumption is 140mA (on chip driver amplifier is not included). Testing results show that the baseband output noise is -70dBm/Hz at the presence of OdBm carrier leakage. The output noise is dominated by the down converted phase noise of carrier leakage. This result gives an instructive conclusion:5. In the direct conversion RFID receiver, the phase noise will be partially cancelled during the down conversion, due to the correlation between the phase noise of carrier leakage and local oscillator for down conversion. In this design, the measured cancellation is about 17dB, which helps the more detailed phase noise requirement of the frequency synthesizer.To verify the chip functionality, a reader prototype is designed which includes reader chip, digital receiver, protocol processor, interfaces, power management and other parts. Testing shows that the prototype can realize complete reader-tag communication. The PC controlled upper machine send the command to reader, process the returned and decoded data, and display the verified EPC code. The longest communication distance is 30cm, when transmitting 20dBm power. Experiments show that beyond the output power, the phase noise of carrier leakage dominates the receiver noise, so increase the output power does not help. To reduce the influence of carrier noise to the receiver is the main task of the future work.更多还原