【作者】 朱志炜；

【导师】 郝跃；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2007， 博士

【摘要】 在IC(集成电路)工业中,ESD(Electro-Static Discharge,静电放电)是影响IC芯片可靠性的主要因素之一,已经成为开发新一代工艺技术的一个难点。在超深亚微米工艺下,缺乏对ESD损伤失效物理机制的理解在很大程度上限制了设计经验从一代工艺传递到下一代工艺,而对失效机理的理解正是超深亚微米工艺ESD保护结构设计的关键。因此,本文主要对超深亚微米CMOS工艺MOSFET的ESD失效物理机制进行了研究。论文首先建立了一个混合模式的仿真平台,为ESD保护结构的研究提供了一个很好的分析和设计工具,同时搭建了一个TLP(传输线脉冲)测试系统,以得到一些细节的数据帮助理解ESD失效机理。本文对ESD应力下超深亚微米NMOSFET器件内部载流子的强电场非本地输运进行了分析和研究,根据其特点可以将电子能量驰豫时间看作是电子能量的函数,然后使用蒙特卡罗模拟方法得到了电子能量驰豫时间和高场迁移率的经验模型,并使用新的参数模型加入ESD混合仿真平台,仿真结果与实验符合较好。最后利用改进的仿真模型对TLP测试的各项关键参数进行了混合模式仿真,详细分析了TLP实验中的若干问题及其物理过程。论文通过对短沟道Silicided(金属硅化物) NMOSFET的研究发现,Silicided扩散区栅侧边缘附近会出现电流集中现象,在源端复合效应的促进下,源端会出现一个不同于漏端的新的热点。这个热点温度甚至可能超过漏端温度,造成NMOSFET的源端热击穿。通过对non-Silicided器件的研究发现,其漏端的镇流电阻可以增加寄生分段BJT的导通均匀性,同时使主要电流通路深入衬底内部,远离Si-SiO2表面,避免了氧化层和表面沟道的过早失效,因此改善了器件的ESD失效阈值。DCGS(漏接触到栅边缘的间距)可以增大镇流电阻,提高ESD失效阈值;但是SCGS(源接触到栅边缘的间距)变大时,源端电阻的增加不利于源衬结的正向导通和分段晶体管的导通均匀性,因此源端镇流电阻增大带来的好处有限。当沟道长度变大时,由于寄生双极晶体管电流增益减小,因此ESD失效电流也减小。论文使用DC和脉冲应力对90nm NMOSFET的ESD潜在损伤进行了测量和分析。分析认为雪崩热空穴注入栅氧化层,会产生界面态和大量中性电子陷阱,引起阈值电压增大、亚阈值电流减小。Snapback应力期间产生的氧化层陷阱将会引起SILC(应力引起的泄漏电流)增加、Qbd(击穿电荷)减少,它也会造成关态漏泄漏电流的退化。HE(热电子)产生的界面态可以在snapback(突发回扫击穿)应力期间屏蔽热空穴注入栅氧化层,导致MOSFET退化速度比未加HE应力的情况小。而栅氧化层损伤不仅在漏区一侧产生,而且也会在源区一侧产生。使用脉冲TLP应力对NMOSFET器件进行测量发现,脉冲周期越长,其退化越大。分析认为这主要是温度效应造成的,脉冲TLP应力周期越长,器件内部温度越高,NMOSFET栅氧化层的注入机制越强,则引起的损伤更大。超深亚微米CMOS工艺的器件特征尺寸小,结深较浅,这就要求ESD保护结构快速开启以顺利的泄放ESD电流的要求。论文最后一部分在以前章节的研究基础上,使用混合仿真方法设计了一款芯片的ESD保护结构。文中采用了ESD检测电路使ESD保护结构更快开启,以避免内部电路损伤。通过混合模式仿真对电路中器件进行了参数调整并验证了保护结构的有效性,测试结果符合设计要求。更多还原

【Abstract】 Electrostatic Discharge (ESD) induced failure is one of the most important reliability problems of the ICs (integrated circuits), which have become one of the most difficult problems for developing the new generation technology. Under the ultra-deep-submicron technology, the absence of understanding on the ESD damage mechanism limits the transfer of the design experience between generations, which is just the key point of the design of the ESD protecting structure. So this paper investigates the ESD failure mechanism of the MOSFET under the ultra-deep-submicron technology.A mixed-mode simulation platform is built up in this paper which serves as an analysis and design tool for the investigation of ESD protection structure. A TLP(Transmission Line Pulse) measurement system is also set up to get further data for the understanding of the ESD failure mechanism. In this paper, the non-local transport of the NMOSFET under high field is analyzed. The electron energy relaxation time can be regarded as the function of the electron energy due to the characteristic of the non-local transport. Then the empiristic model of the electron energy relaxation time and high field mobility can be got by the Monte Carlo simulation. At last the new parameter models are integrated into the mixed-mode simulation system and the simulation results shows the accordance with the experiment. The critical parameters of the TLP measurement are simulated by the modified simulation model, in which several problems and physical mechanisms are investigated at length.The investigation of short channel silicided NMOSFETs shows that the current crowd is appeared in the silicided diffusion edge. With the help of the recombination in the source region, the new hot spot can be found in the source region, whose temperature can even exceed that in the drain region and cause the thermal breakdown of the MOSFETs. The ballasting resistance of the non-Silicided device can enhance the turning on uniformity, which helps to lead the main current path far away from the channel surface and avoid the early failure. The increase of DCGS(Drain Contact to Gate Space) is a way to increase the ballasting resistance, and may improve the ESD failure threshold. However, when the SCGS(Source Contact to Gate Space) increase, the increase of the source resistance goes against the forward turning on and reduces the uniformity of the segmented BJT, so the benefit of ballasting resistance is restrained. In addition, increasing the channel length can decrease the failure current for the current gain of the parasitic BJT’s decreases.The measurement and analysis to the ESD latent damage in 90nm technology are performed under the DC and pulse stress. The results show that when the avalanche hot holes inject into oxide, interface states and neutral electron traps are generated, and then threshold voltage increases and sub-threshold current decreases. The increase of the oxide neutral electron traps can cause the increase of SILC(Stress Induced Leakage Current), the decrease of the breakdown charges and the degeneration of the off-state drain leakage current. The generated interface states during the HE(Hot Electron) stress can shield the injection of the hot holes and lead to lower degradation speed than that of the fresh device. Stress induced oxide damage located not only in the region near the drain, but also in the region near the source. The measurement of the MOSFET under the pulsed TLP stress shows that the longer the pulse duration is, the more the degradation there would be, where the temperature effect is the main reason. It means the longer duration of the TLP stress has, the higher temperature the device may generates, which means the stronger injection mechanism and the more severe damage to the ICs.The ultra-deep-submicron CMOS devices have the shallow junction depth and small size. So the ESD protection structure must turn on quickly to shunt the ESD current. Based on the former investigation, one ESD protection structure is designed using the mixed-mode simulation in the last part of this dissertation. The ESD detected circuit is used to quicken the turn on of the ESD protection structure to avoid the damage of the core circuit. The parameters are adjusted and the validation of the protection structure is verified by the mixed-mode simulation. The test results accord with the design requirement.更多还原