全模式国标数字电视解调芯片研究与设计

【作者】 巫建明；

【导师】 闵昊；

【作者基本信息】 复旦大学 ， 微电子与固体电子学， 2008， 博士

【摘要】 数字电视技术正在全世界范围内掀起新一轮产业革命,它将带来用户收听广播电视的根本性变革,并对整个信息产业的发展产生深远影响。美国、欧洲、日本、韩国都已相继开播了数字电视节目,中国也将于2008年奥运会期间在八个奥运城市开播地面高清数字电视节目。目前作为数字电视地面广播系统核心技术的解调芯片成为众多机构的研发重点。本论文针对国标数字电视地面多媒体广播(DTMB)标准中包含单载波和多载波两种传输模式的现状,提出一套同时支持DTMB系统单多载波传输模式的解调算法,并针对VLSI芯片低复杂度的设计目标提出一套优化的全模式国标数字电视解调芯片架构。首先,在分析三种主流的宽带无线通信接收机架构的基础上,本文通过系统架构级的分析研究,提出一种能同时兼容单多载波信号处理的全模式解调芯片架构。该架构在单多载波两种模式下能有效地实现硬件资源共享,并具有统一的信号处理流程。接着,本文深入研究了DTMB系统中的同步和信道估计与均衡算法,提出了以下几种新颖的算法和硬件结构来提高解调芯片的性能指标:(1)针对现有的帧同步算法无法在大载波频偏条件下工作的问题,本文提出一种新型的载波频偏粗估计算法,该算法利用PN序列的“移位加”特性恢复出PN序列的自相关特性,并通过相关峰的相位信息来提取出载波频偏。(2)针对动态信道下的同步跟踪提出一种有效的相关峰跟踪策略,来减小动态信道下的漏警和误警概率。同时针对现有采样频偏估计算法捕获范围较小的问题,提出一种改进算法以支持更大的采样频偏,该算法在现有算法基础上结合相关峰漂移来联合给出采样频偏估计。(3)针对短时延信道下的基于PN序列循环相关的信道估计方案,本文提出一种基于快速哈德马特变换(FHT)的循环相关器实现结构,与传统的基于匹配滤波器的循环相关器结构相比,所提出的新方法能够大大减少运算次数,从而减少硬件开销和运算功耗。(4)现有的应用于长时延信道的信道估计方案需要进行多次迭代,并且需要多个大点数FFT运算单元,本文提出基于一次迭代的优化硬件实现方案,通过复用FFT运算单元、重构帧体数据与信道冲激响应的循环卷积等方法来有效降低硬件实现复杂度。最后,本文在综合前述的各种改进算法和硬件电路结构的基础上,完整地提出了DTMB全模式解调芯片的解调算法以及解调芯片的VLSI构架,并详细分析数据通路和信号处流流程,并对单多载波模式下各子模块的复用情况进行了分析。随后介绍了一种适用于数字电视解调芯片设计验证的FPGA测试平台,并基于该平台完成了DTMB全模式解调器的各项性能指标的测试。测试结果表明本文所提出的各种算法和VLSI电路结构均达到预期的设计要求,具有良好的实际应用价值。更多还原

【Abstract】 Digital television technology is bringing up a new industry revolution worldwide. It will ultimately change the style of broadcasting programs, and meanwhile exercise a profound influence upon the development of information industry. America, Europe, Japan and Korea has offered DTV service one after the other, and China will start delivering DTV programs at the eight host cities during the 2008 Beijing Olympics. Therefore, the baseband demodulation chip, which is regarded as the kernel component of DTV system, has become intensive focus of many research institutes.This work is targeting at the demodulation chip design of China DTTB standard, which supports two transmission modes: single carrier modulation (SCM) technique and multi-carrier modulation (MCM) technique. And a novel demodulation algorithm capable of processing both SCM and MCM signals is presented. Meanwhile an optimized dual-mode demodulator architecture with low-complexity VLSI implementation cost is developed.Firstly, based on comparisons of mainstream broadband wireless communication receiver architecture and system level analysis, a dual-mode receiver architecture compatible with both SCM and MCM modes is proposed in this dissertation. The proposed architecture can realize efficient hardware sharing under two working modes, and shares the same signal processing flow.Secondly, several new demodulation algorithms and corresponding hardware structure are proposed to improve the whole demodulator performance upon in-depth investigation of synchronization, channel estimation and equalization algorithm of DTMB system. (1) The existing frame synchronization algorithm could not work properly when a large carrier frequency offset exists. A new coarse frequency estimation method is presented utilizing the shift-and-add property of PN sequence to recover the delta-like auto-correlation function of PN sequence. The coarse carrier frequency offset can be retrieved from the phase of the reconstructed correlation peak. (2) A dynamic tracking algorithm is presented to achieve robust frame synchronization path under dynamic multipath fading channel. Simulation results show that to reduce miss alarm and false detection probability. Also a new sampling offset estimation algorithm with larger estimation range is developed. The improved algorithm combines the correlation peak shift and existing method to provide actual sampling offset estimation. (3) A novel FHT-based cyclic correlator is proposed instead of the traditional matched-filter based cyclic correlator under short-echo multipath channel. The proposed architecture can greatly save area cost and power consumption due to the reduction of needed operations compared with matched filter architecture. (4) The existing channel estimation method needs several iterations and several large-point FFT units to for long-echo multipath channel. In this dissertation a novel hardware architecture which only iterates once is adopted and cyclic convolution is constructed between frame body and channel impulse response to effectively reduce hardware complexity.Finally, a complete dual mode DTMB demodulator architecture is developed on the basis of aforementioned algorithms and hardware structure. Detailed analysis of the VLSI architecture, datapath and signal processing flow, as well as module reuse information is illustrated. Then a general FPGA verification platform for DTV system is introduced and the FPGA receiver compliant with DTMB standard is tested on the above platform. The test results show that the proposed algorithms and VLSI circuit structure achieve the design requirements and has promising application value.更多还原