【作者】 郭杰荣；

【导师】 何怡刚；

【作者基本信息】 湖南大学 ， 电气工程， 2008， 博士

【摘要】 开关电流(Switched Current, SI)技术是20世纪80年代末提出的一门完全采用数字CMOS工艺技术的模拟取样数据信号处理技术,它利用MOS晶体管在其栅极开路时通过存储在栅极氧化电容上的电荷维持其漏极电流。开关电流技术不需要线性电容和高性能的运算放大器,可与标准数字CMOS工艺兼容,而且,它还具有低电压、高速、宽带、小面积等优点,自问世以来就引起了国内外相关学者的高度关注,并得到了较快发展。开关电流技术是继开关电容技术之后的一种新的模拟取样数据信号处理技术,同时也是数字/模拟混合集成VLSI实现的一个重要发展方向。在开关电流电路的测试方面几乎是空白,现有的模拟电路测试方法并不适合开关电流电路。目前有很少的关于开关电流测试的文献,讨论测试原理、过程以及BIST和DFT,如开关电流四乘幂滤波器振荡能力的测试方法,基于直流信号的开关电流流水线结构AD转换器的测试方法,利用改变时钟顺序将二分电路结构重组为串连电流镜结构并将输入与输出直流信号进行对比的方法。提出的方法都只适用于某一特定电路结构和只能测试部分电路功能或特定结构,对于参数性故障或缺陷、估计信号的容差等都讨论不多。本文分析和总结了已有开关电流测试方法,开发了开关电流非理想因素行为模拟软件系统,研究了开关电流测试用故障模型,提出了几种测试理论,主要工作包括:1.系统研究了开关电流非理想特性,讨论了各类仿真工具在开关电流电路仿真分析中的优缺点,提出一种基于SIMULINK的系列行为仿真模型,可以在短时间内在高级别对SI系统进行行为仿真。模型考虑了ΣΔ调制器各种非理想因素,如电荷注入误差、输入输出电导比误差、调整误差噪声误差等以及晶体管模型参数与误差的关系。2.研究了当前模拟电路测试的困难。针对开关电流电路的构成方式及全晶体管结构特点,提出一种较为完整的故障模型,可用于多种测试方法。研究了MOS管参数群组的方式并进行了实例分析。介绍了开关电流仿真软件ASIZ及其基本功能及特点。3.研究了开关电流电路的节点分析与基于跨导的灵敏度分析,可以在电路设计过程中为设计的精确性提供优化的参数选择并对性能结果进行预测。针对开关电流电路的失配效应与电流定标误差引起的电路性能偏差,在给定的跨导随机误差的条件下计算了绝对或统计偏差,进一步获得误差容限,可将其用于成品电路的测试。对开关电流电路的失配效应进行了实例测试。4.提出一种适用于开关电流电路的伪随机测试方法。讨论了伪随机测试技术在开关电流电路中测试中的应用。对伪随机激励信号的产生及其与被测开关电流电路z域传输函数的适配进行了分析,论述了基于相关函数分析在性能空间到识别信号空间中可接受容差空间进行容差范围映射的方法,以及测试技术的相对可置信度分析。5.提出了一种基于时域与频域中多尺度小波分分解及神经网络非线性映射归纳的对模拟集成开关电流电路进行故障缺陷测试的方法。包括以下步骤:针对典型故障情况,以选择的正弦信号作为激励信号,电路输出的信号在时域和频域中分别采样作为神经网络训练样本;利用开关电流电路结构特性,采用群组灵敏度分析选择确定测试缺陷点;为降低神经网络的复杂性,采用小波多尺度分解对各类响应数据进行预处理,产生故障细貌后在输入神经网络;神经网络用于将不同的缺陷响应结果分类、识别。测量待测电路的实际电压信号,将其输入训练好的神经网络模型,完成故障测试与识别。更多还原

【Abstract】 Switching Current (Switched Current SI) technology is a simulation sampling data signal processing technology completely adopt digital CMOS process technology which has been bring forward by the late 1980s . It uses MOS transistors to maintain its current capacity, through storage the drain charge in the gate capacitance of its open gate Switched Current technology does not require switching linear capacitance and high-performance operational amplifiers and compatible with standard digital CMOS process completely. It also has the advantages of low-voltage, high-speed, broadband, small size. Since it advent related scholars of home and abroad are arosed high degree of concern, and has been relatively rapid development. Switched current technology is a new simulation sampling data signal processing technology follow the switched-capacitor technology, as well as an important direction of development of digital / analog hybrid integrated VLSI Implementation.However, concerning the testing aspect, the test techniques proposed for analog circuits are not readily applicable to SI circuits. To date, little has been published on the test of SI circuits. Literatures describe reconfiguration of SI biquadrates filters for test, Built-In Self-Test (BIST) scheme, Design Function Test(DFT), testing methods Based on the DC signal pipeline structure AD switching current converter, restructuring of current mirror structure use clock change and contrast between the DC input signals and output. The proposed techniques suffer of being applicable only to some specific structures, and these methods only use DC and low-frequency parameters for implicit functional testing, the tolerate range and failure or error in parameters have not been discussed.This paper summarizes the existing analysis and test methods of switching current circuits, developed a system simulation software on switching current non-ideal factors , investigate the fault model of Switch current circuits, Several test theory put forward. Its main tasks are:1. Invesitigate non-ideal characteristics of switched current circuits systematacially, discussed the shortcomings of various simulation tools for the switch current circuit simulation analysis. A complete set of SIMULINK models based on non-ideal of switched-current circuit is presented, which allow exhaustive behavioral simulations of switched current to be performed. The proposed set of models takes into accounts most of the SI memory non-idealities, such as charge injection errors, conductance ratio error, settling error, kT/C noise, and a description of the relationship between error and parameters of MOS FET is presented.2. Research on the test difficulties on current analog circuit, Aim at switch current circuit form and the entire structure of transistors, a more comprehensive fault model is put forward, which is applicable for multiform test methods. Chohort MOS parameters is studied and analyzed in instance. The basic functions and features of switching current ASIZ simulation software is introduced.3. Switched current circuit on the nodal analysis and the sensitivity analysis based on transconductance are investigated, whitch can provide choice for optimized performance parameters and the results forecast in the design process. Based on mismatch effect and circuit performance deviation error caused by current scaling, under the conditions of given the transconductance random error absolute or statistical error is calculated, further achieve the error tolerance, whitch can be used to test circuit products.4. A built in Pseudo-Random sequence testing for testing embedded switched-current filters is described. The generation approach of Pseudo-Random sequence and the match for z functions of switched-current filters is analyzed and calculated. Based on the correlation function of the performance space to identification signals space acceptable tolerances space tolerance of mapping methods is discussed, And the relative Confidence level of testing technical is analyzed.5. Combining the time and frequency location and multiple-scale analysis of Wavelet transform (WT) with the nonlinear mapping and generalizing of Neural Network, an efficient defect-oriented parametric test method for switched-current integrated circuits is proposed. Include the following steps: sinusoidal input to the analog circuits as stimuli and its output was sampled in frequency and time domain to collect training data for neural network. Chohort sensitivity analysis is applied for selecting the test models. To reduce complexity of the neural network, the collected data was processed by WT to draw energy features, generate fault features using wavelet decomposition to process the response drastically reduce the number of input fed to the Neural Network, simplifying its architecture and minimizing its training and processing time for detecting hard-detectable catastrophic defects in switched-current circuits.更多还原