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DVB-T COFDM接收系统中关键技术研究与设计

Study and Design of Key Technologies for DVB-T COFDM Receiver Systems

【作者】 周加铳

【导师】 陈咏恩;

【作者基本信息】 同济大学 , 控制理论与控制工程, 2007, 博士

【摘要】 地面数字视频广播(Digital Video Broadcasting-Terrestrial,DVB-T)作为当今世界最主要的数字电视地面传输标准之一,其采用编码正交频分复用(CodedOrthogonal Frequency Division Multiplexing,COFDM)技术进行调制,是一种典型的OFDM系统。OFDM技术具有抗多径干扰能力强、频谱利用率高等诸多优点,应用前景非常广阔;但是OFDM系统对同步误差和信道估计误差比较敏感,如何快速可靠的实现系统同步和信道估计对接收系统来说非常重要。本文将重点研究DVB-T COFDM接收中的定时同步、载波同步和信道估计等关键技术难点,给出适合DVB-T系统应用的解决方法。主要内容包括:(1)首先简要介绍地面无线信道的基本特性和OFDM技术基本原理,建立了完整的DVB-T系统传输模型;通过分析各种非理想因素对系统性能的影响,设计了一种采用捕获和跟踪两级同步机制及时频级联信道估计技术的内接收机方案。(2)分析了基于循环前缀和导频的定时同步方法的性能。根据循环前缀的重复特性,实现传输模式/保护间隔类型检测、时域符号粗同步和小数倍子载波频偏估计各模块的复用,并应用截短相关长度及门限方法提高估计性能;根据导频的功率特性,设计了一种简单快速的符号类型检测方法;根据导频相关和的相位特性确定了适当的符号精同步方案,将符号内导频相关与符号间导频相关相结合,在保证精度的同时扩大了估计范围;根据最小平方准则实现采样时钟频偏与剩余载波频偏的联合估计,克服了系统中连续导频分布不对称的缺点。(3)提出了一种基于保护带功率检测和连续导频相关的两级整数倍频偏估计新方案;第一级判断整数倍频偏的正负,降低一半计算复杂度;第二级采用部分连续导频估计整数倍频偏,估计性能变化不大但复杂度大大降低。(4)在研究现有估计方法的基础上,确定了时频级联的信道估计。通过对导频位置LS估计结果进行自适应滤波,大大降低了噪声影响;针对非导频位置应用传统DFT方法存在的缺憾,给出了基于变换域方法、两种DCT/IDCT变换法及时域迭代处理等多种改进方法;在分析各种插值算法性能的基础上,设计了一种低复杂度的实现方案。(5)确定了系统同步和信道估计各模块的结构;提出了一种新的基16/8混合基FFT实现结构,采用单个基16/8复用的蝶形运算单元顺序处理,并通过减少乘法器数目,有效降低硬件消耗;运算单元内部采用“基4+基4/2”级联流水线方式,大大加快运算速度;此外,应用对称乒乓RAM结构提高了蝶形运算单元的连续运算能力;并且使用改进的块浮点防溢出机制保证运算精度。(6)最后简单讨论了进一步工作的方向。

【Abstract】 Digital Video Broadcasting-Terrestrial (DVB-T) has been one of the most important standards for terrestrial transmission and undoubtedly been shown as a great success in delivering high quality digital television. DVB-T adopts coded orthogonal frequency division multiplexing (COFDM) as the modulation technique and is a typical OFDM system. OFDM has found its wide application in many scientific areas due to its high-spectrum efficiency, its robustness against both multi-path and pulse noises, etc. However, the OFDM system is vulnerable to synchronization errors and channel estimation errors. How to effectively do the synchronization and do the channel estimation at the OFDM receiver are important issues, which need be addressed in OFDM systems. Hence, the dissertation focuses on the timing synchronization, carrier frequency synchronization and channel estimation methods design for DVB-T. The main contribution of this dissertation can be concluded as following:Firstly, this dissertation gives a brief introduction about the characteristics of the terrestrial wireless channels and basic principles about OFDM technologies. A complete DVB-T transmission system model is established and the effects of non-ideal transmission conditions are thoroughly analyzed. A inner receiver scheme, consists of two-stage synchronization (acquisition and tracking) and two-dimension channel estimation, is adopted.Secondly, in this dissertation, a whole timing synchronization scheme including symbol synchronization and sampling clock synchronization is presented. Employing cyclic property of GI, the blind Mode/GI detection, coarse symbol synchronization and fractional frequency offset are exploited. For more accurate symbol timing, we will illustrate the pilot phase property. In sampling clock synchronization, an estimation based on least square algorithm with the multi-stage tracking loop is proposed which improved the conventional designs.Thirdly, a two-stage scheme is proposed for the integer carrier frequency offset acquisition to reduce the search range. Besides, two low complexity methods are also proposed to detect the accurate integer carrier frequency offset value and many multiplications can be saved without any performance loss to the overall system compared with the conventional approach.Fourthly, we propose the adaptive channel estimator for pilot signal which can average out the noise effects under portable environments. Furthermore, the channel response is estimated by means of two-dimension interpolation of scattered pilots. We analyze several polynomial interpolation methods under channels specified by standards.Fifthly, A novel mixed radix-16/8 FFT algorithm and architecture are presented. By using a single radix-16/8 butterfly processing element and reducing the number of multipliers, the proposed approach obtained significant hardware reduction. To achieve high speed processing, the "radix-4+radix-4/2" cascade pipeline architecture is designed in radix-16/8 butterfly unit. Furthermore, a symmetry ping-pang RAM structure is adopted to increase the continuous computing capability of the butterfly core. Computing precision is also enhanced through a modified block floating point anti-overflow scheme.Finally, the problems requiring further studies are discussed.

  • 【网络出版投稿人】 同济大学
  • 【网络出版年期】2008年 04期
  • 【分类号】TN919.3;TN948.55
  • 【被引频次】23
  • 【下载频次】849
  • 攻读期成果
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