刻蚀衍射光栅波分复用器仿真与优化设计

【作者】 宋军；

【导师】 何赛灵；

【作者基本信息】 浙江大学 ， 光学工程， 2007， 博士

【摘要】 在光通讯网络里，随着波分复用技术的使用，可获得的信息容量迅速增加。波分复用器／解复用器是波分复用网络里最关键、最核心的器件。而这其中基于平面波导集成技术设计制作的刻蚀衍射光栅器件，由于具有结构紧凑、光谱性能优异等显著优势，成为其中具有广泛应用潜力的一种。然而由于器件采用了凹面结构，且光栅周期可变，从而使得对这样的器件精确计算和设计非常困难，特别在此前研究中一直不能对该类器件偏振特性进行有效分析。本论文首先对使用不同光栅结构的刻蚀衍射光栅器件基于电磁理论做了精确的仿真模拟。采用对镀金属光栅和全内反射光栅都适用的边界元方法，精确分析了器件结构参数对损耗、偏振相关损耗、串扰、回波损耗、色散等关键性能的影响，探讨了器件损耗和偏振相关损耗的起源；而对镀金属光栅，又提出了更高效的矩量法做仿真分析，并对特定的性能要求给出了器件结构参数确定的方法；对全内反射光栅则在考虑了Goos-Hanchen位移和齿面有限尺寸影响后对标量算法进行修正，提出了快速又精确的分析方法，该方法使用简单的解析推导，既能取得与边界元算法接近的计算精度，又可以对计算结果给予满意的物理解释。出于改进器件性能的要求，论文提出了许多新颖的器件改进设计方法，这主要包括：(1)平顶低色散刻蚀衍射光栅设计：在输入波导末端加上一段带有预整形输入的多模干涉区，用优化设计的预整形结构来让频谱具有陡峭的边缘，通过基因算法来优化抛物线形多模干涉区结构，获得了频谱高平坦(有效带宽比接近85％)、低带通纹波(接近0dB)、低色散(低于3ps／nm)的刻蚀衍射光栅设计。(2)低偏振相关损耗设计：靠让光栅阴影面具有适当的粗糙度，可以在很大波长范围内设计具有低于0.2dB的偏振相关损耗的刻蚀衍射光栅。靠让光栅具有合适的圆角半径或阴影面倾斜度，可以设计在中心波长附近一定带宽内具有低偏振相关损耗的刻蚀衍射光栅。(3)低串扰设计：在每个输出波导前端引入两个结构优化的空气槽，以此来对两相邻波长在该通道处的旁瓣场分布作强烈共振散射，却对工作波长场分布有小的影响。这样可以大大抑制相邻通道旁瓣影响，设计串扰50dB以下的刻蚀衍射光栅器件。(4)低回波损耗设计：在将刻蚀衍射光栅输入波导放置在中心波长衍射包络能量极小值位置后，进一步通过交替变换齿面衍射级分布，可以抑制相邻衍射级能量分布，减小其对输入波导可能带来的回波损耗，至40dB左右。(5)大光栅齿面大自由光谱范围设计：对刻蚀衍射光栅器件，选用大的衍射级，可以获得相对较大的光栅齿面，减小制作难度，同时可让器件的损耗和偏振敏感性都降低；然而大的衍射级必然降低器件的自由光谱范围，使波分复用可以利用的通道数减少。论文通过对刻蚀衍射光栅所有齿面衍射级全局优化，将使用衍射包络对相邻两衍射包络消光比提高到30dB以上，使得相邻衍射包络的能量可以被当作可接受的串扰看待，进而解决了上述矛盾。详尽分析了光栅圆角化、表面粗糙以及波导和器件自由扩散区点缺陷存在等工艺误差对器件性能带来的影响，为器件制作提供了参考。对设计好的集成波导器件，本论文分别采用硅基二氧化硅波导结构，实现了器件制作的全部工艺研究，并实现了器件样品的制作。通过性能的测试，为器件制作工艺的改进提供了参考。更多还原

【Abstract】 With the use of Wavelength Division Multiplexing (WM) technology, the information capacity of an optical communication network is greatly increased.Wavelength multiplexers and demultiplexers are key components in a WDM optical network. Among various technologies to implement the multiplexing/demultiplexing functionality, etched diffraction gratings (EDGs) have shown great potential due to their compactness and high spectral finesse. Conventional numerical method of grating simulations cannot be used to simulate a concave grating with a large size in terms of the wavelength. Moreover, the essential polarization dependent characteristics of the diffraction grating cannot be treated with the scalar method.Therefore, one needs a more accurate simulation tool which can take the polarization effects of EDGs into consideration.In this thesis, the polarization dependent characteristics of an etched diffraction grating demultiplexer are analyzed using the boundary element method (BEM) for both an echelle grating coated with a metal and a dielectric grating with retro-reflecting facets. For EDGs with a metal coated, a more effective method of moment (MoM) is also presented to calculate the surface current, which produces the diffracted field at the image plane, for both polarizations. Futhermore, a fast simulation method for EDGs with retro-reflecting facets is presented based on the Kirchhoff-Huygens principle and the Goos-Hanchen shift. The simple method has a good agreement with a BEM for a wide range of practical device parameters. Using these numerical methods, many performances of the device (e.g., loss, polarization dependent loss, crosstalk, chromatic dispersion, return loss) are analyzed detailed and an insightful physical explanation for the numerical results are also given.Some novel designs are presented in order to improve performances of EDGs. These designs are as follows: (1) A flat-topped EDG demultiplexer with low chromatic dispersion is designed. A parabolic multimode interference (MMI) section with a reshaping taper is connected at the end of the input waveguide. The field distribution at the end of the taper is reshaped optimally to have sharp transitions. A genetic algorithm is used to optimize the parabolic MMI section. The designed EDG demultiplexer has an excellent fiat-topped spectral response and a very low chromatic dispersion characteristic. (2) By making the surface of shaded facets with an appropriate roughness, the PDL of the demultiplexer can effectively be improved in a large bandwith. The PDL of an EDG demultiplexer can be reduced near the central wavelength at some special values for the radius of the rounded comers (or with special values for the tilting of shaded facets). (3)An EDG demultiplexer with high sidelobe suppression is designed. Sidelobes resulting from two adjacent wavelengths are suppressed by etching two optimized rectangular air trenches in front of each output waveguide, which can induce large resonance loss to the adjacent wavelength whereas have little influence on the operation wavelength. The designed EDG demultiplexer can present a crosstalk as small as 50 dB in theory. (4) A design for EDG demultiplexers is presented to reduce the return loss. The input waveguide is placed on the minimal intensity position of the diffraction envelope. Then, by further chirping the diffraction order for each facet, we minimize the envelope intensity for other adjacent diffraction orders, which can contribute to a negligible return loss for a large spectral width. (5) A design for EDG demultiplexers is presented to obtain both large grating facets and a larger free spectral range (FSR) using the optimal chirped diffraction orders for different facets. The large grating facets by using a large diffraction order contribute to lowering the manufacturing difficulty, and can provide lower polarization dependent loss. However, usually the large diffraction order must lower the FSR of the device by all means. Based on the present design, the FSR can overlay the whole diffraction envelop for a special order, but avoid the influence of the adjacent diffraction envelops. Calculations indicate that the extinction ratio between the operated order and adjacent orders can attain a 35 dB or so, which makes the crosstalk from channels in adjacent envelops to those in the operated diffraction envelop acceptable.The fabrication tolerances (e.g., rounded effect, surface roughness and point defect in the waveguid) to the performance (such as the insertion loss, the polarization dependent loss and the chromatic dispersion) of an EDG demultiplexer are detailed analyzed in the thesis. Based on silica on silicon, all the manufacture processes are implemented. At last the fabricating of some EDG chip samples is made. Some measurements are helpful for imporved fabrications in future.更多还原