【作者】 易会战；

【导师】 杨学军；

【作者基本信息】 国防科学技术大学 ， 计算机科学与技术， 2006， 博士

【摘要】 计算机系统的功耗问题是计算机技术进一步发展亟待解决的问题之一。功耗急剧增长提高了芯片的封装和制冷成本。高温环境下执行增加了芯片的失效率,导致计算机系统的可靠性下降。嵌入式移动计算技术是芯片行业最活跃的领域,嵌入式的移动设备往往依靠电池供电,电池的供电时间是系统的重要参数之一。与半导体技术的发展速度相比电池技术的发展缓慢,未来的移动设备必须在有限能量供应下发挥更大的效能,对系统能量消耗有很高的要求。信息行业的设备消耗了大量能量,并且能量消耗呈现逐年增长的趋势。大量的能量消耗要求系统采用有效的能量管理策略提高能量的使用效率。因此,不管是嵌入式移动设备还是高性能系统,都必须考虑功耗问题。从底层的电路技术,到逻辑技术、体系结构技术和高层的软件技术,出现了各种方法用于降低计算机系统的能量消耗。本文重点研究用体系结构设计和编译器指导的方法减少计算机系统的能量消耗。体系结构是软件和硬件的接口,对于低层的低功耗硬件设计和上层的软件低功耗优化都有重要的影响,本文分析了传统体系结构的能量效率变化趋势,提出今后的体系结构低功耗设计的思路之一是采用并行处理技术。当前新的硬件技术—动态电压调节(DVS)和部件动态关闭(TOSU)—为软件低功耗优化提供了手段,本文的工作基于编译器的静态分析或者profile技术,获得应用对系统资源的使用特性,使用DVS或者TOSU技术减少计算机系统的能量消耗。具体说来,本文包括三部分的研究工作:首先研究了微处理器体系结构的能量有效性;然后研究了实时系统的能量有效性优化方法;最后研究了并行系统的能量有效性优化方法。本文的主要创新如下:1、提出了微处理器的体系结构能量有效性模型,克服了传统的能量有效性模型受工艺参数和电压参数影响的问题,该模型能有效地评估体系结构设计对能量有效性的影响。通过对典型微处理器的分析,验证了该模型的合理性。通过该模型分析了体系结构设计的多种典型技术,得出了并行处理技术和部件使用局部化是提高能量有效性的主要方法。指导了本课题的研究。2、提出了面向程序的剩余最差时间分析方法,克服了过去动态电压调节技术的研究结果不能紧密结合时间估计技术的问题,给出了动态电压调节算法实现的总体框架,建立了性能/功耗模拟环境RTLPower,嵌入式程序集的测试证明该算法最大能够节省50%的能量。3、提出了等比例电压调节点的优化放置方法—OPOT和OPTO,OPOT给出了无开销情况下的最优调节点放置方法,并给出了证明,OPTO给出了存在开销情况下的调节点优化放置方法,嵌入式程序集的测试证明两种调节点优化放置方法有效的减少了能量消耗。4、提出了确定执行模式的最优频率设置指导的贪婪电压调节方法和最高频率限制情况下确定执行模式的最优频率设置指导的贪婪电压调节方法,克服了过去电压调节方法不能有效利用松弛时间的问题,能够最佳地设置每阶段的频率,模拟实验结果验证了两种电压调节方法的有效性。5、提出了编译器指导的DVS并行系统的能量和性能权衡技术,针对MPI消息传递应用使用编译器自动构造通信和计算区域,为这些区域分配最优的电压/频率,克服了过去的研究完全采用手工方法的问题,建立了性能/功耗的并行模拟环境MIPSpar,并行MPI程序集的测试证明该技术在性能损失不超过5%的情况下,能够节省20~40%的能量消耗。6、提出了编译器指导的并行系统通信链路的动态关闭技术,编译器将并行程序划分为通信区间和计算区间,使用链路打开/关闭指令动态改变通信链路的状态,克服了基于网络链路利用率的预测方式不可避免地引入的链路打开/关闭开销,模拟实验结果表明在小于1%的网络延迟和性能损失下,减少了20~70%的互连网络能量消耗。更多还原

【Abstract】 Power consumption has become an obstruction in the road to higher-performance computer systems. First of all, the continuing growth of power consumption has increased the packaging and cooling cost. In addition, the higher temperature accentuates a large number of failure mechanisms in integrated circuits (ICs) and causes frequent failure of computer systems.Embedded systems for mobile computing are developing rapidly, and a crucial parameter of mobile systems is the continued time of energy supply. Although the performance in ICs has been increasing rapidly in recent years, battery techniques are developed slowly. So it is of significant importance for battery-powered mobile systems to use more effective low-power techniques.The energy consumption by the facilities from IT industry has been steadily growing year by year and large quantities of energy consumption necessitate power management to improve energy efficiency. So it is very imperative not only for mobile systems but also for high-performance systems to develop effective low-power techniques.Quantities of novel low-power techniques at different levels including circuit, logic, architecture and software levels, in order of increasing abstraction, have been proposed to reduce energy consumption. This thesis aims at reducing energy consumption by architecture design and compiler optimization. First of all, the architecture is the interface between software and hardware, and significantly affects low power hardware design and software-directed power management. So energy efficiency of microprocessor architecture is investigated, and parallel processing is analyzed as an energy-efficient architecture technique. Secondly, new hardware techniques such as dynamic voltage scaling (DVS) and turning off unused system units (TOSU) have come forward, and are widely used by the software-directed work in the thesis. In sum, the thesis consists of three parts: the first is to investigate energy efficiency of microprocessor architecture; the second is to present some methods of energy optimization in real-time systems; the last is to give some methods of energy optimization in parallel systems. The main contributions of the thesis are as follows:1. A model on energy efficiency of microprocessor architecture is proposed. Since it eliminates the influence of technology and voltage, the model can be used to evaluate energy efficiency of different architecture designs. The analytical results of typical microprocessors show the model is a reasonable metric of energy efficiency. By model analyses of multiple architecture techniques, the results show that parallel processing and localizing the use of system units are primary solutions improving energy efficiency. 2. A dynamic voltage scaling method integrated with estimation of the reduced worst-case execution time is proposed in detail. Compared with the past work, dynamic voltage scaling and WCET (worst-case execution time) analysis combine to a united frame, and a simulation environment named RTLPower is the realization result. The simulation results from embedded applications show the new dynamic voltage scaling method can obtain energy reduction of up to 50% over no power management.3. Two optimizing placement methods of dynamic voltage scaling points, OPOT and OPTO, are proposed. OPOT is declared as an optimal placement method without time overhead and is proved, OPTO is an optimizing placement method. The simulation results from embedded applications show two methods reduce energy consumption effectively.4. Two real-time voltage adjustment schemes are proposed. One is a voltage adjustment scheme directed by the optimal frequency configuration of fixed execution pattern, and the other further considers the maximum frequency of system. Compared with the past voltage schemes, the new schemes can make use of the slack time more efficiently. The simulation results from synthetic applications show the new schemes can obtain the largest energy reduction.5. Compiler-directed energy-time tradeoff on DVS-enabled parallel systems is proposed. Compared with the past work, the new method has used compiler techniques to automatically form communication regions and computation regions, and the optimal frequency and voltage are assigned to each region by solving a 0-1 integer-programming problem. A performance/power parallel simulation environment, MIPSpar, is established, and the simulation results from MPI benchmark applications show that the method can save 20~40% energy consumption with less than 5% performance degradation.6. A technique of compiler-directed power-aware on/off network links is proposed. Compared with the past history-based work, the new technique has used compiler techniques to automatically divide MPI applications into communication intervals and computation intervals, and avoided time overhead of state switching. The simulation results from MPI applications show that the proposed compiler-directed method can reduce energy consumption of interconnection networks by 20~70%, at a loss of less than 1% network latency and performance degradation.更多还原