【作者】 张晓明；

【导师】 张民选； 孙志刚；

【作者基本信息】 国防科学技术大学 ， 计算机科学与技术， 2006， 博士

【摘要】 为支持不断增长的网络应用业务,网络设备越来越呈现出智能化处理特点。智能化处理不仅要求网络设备具有多层交换、安全处理和流量管理等功能,还必须具有强大的协议处理能力和灵活的可编程性,能够快速适应新型业务的添加和配置。因此,基于ASIP(Application Specific Instruction Processor)技术的网络处理器在网络设备中得到了广泛的应用,成为推动下一代互联网发展的核心器件。本文以网络处理器系统设计与实现为目标,从系统设计的角度研究网络处理器的早期设计和性能评价方法,并深入研究了网络处理器中若干关键的实现技术。主要创新点包括:(1)针对网络处理器设计评价和方案优选困难的问题,结合MPSoC(Multi-ProcessorSystem on Chip)系统设计和网络报文处理特点,提出了网络处理器设计空间开发框架YH-NPDF(YinHe Network Processor Design Framework)。该框架基于平台化设计思想,采用反应式数据流进程网络RDPN(Reactive Dataflow Process Network)描述网络应用,并与参数化硬件体系结构模型相结合评价网络处理器的处理性能,通过整体退火遗传算法快速搜索设计空间和优选系统设计方案。YH-NPDF在网络应用建模、硬件资源模型和设计方案优选等方面能够较好地适应网络处理器设计和开发中的智能化报文处理需求。(2)针对并行结构的网络处理器,提出基于模糊反馈控制环(F2CL,Fuzzy FeedbackControl Loop)的报文并行调度算法。该算法使用F2CL机制改善系统负载均衡状况;采用流cache缓存报文流的调度信息,在负载不均衡时优选调节重负载流,在流超时情况下允许对同一流内的后继报文实施重映射,从而有效控制报文乱序。实验结果表明,该算法能够在保持负载均衡的同时获得较好的报文保序效果,综合性能优于目前已有的同类算法。(3)针对网络处理器中报文缓冲的特点,提出基于流水输入/并行输出(PIPO,Pipelining Input and Parallel Output)的多通道报文缓冲结构。PIPO采用流水输入调度技术处理输入端的写请求序列,采用并行输出调度技术调度输出端的读请求序列,同时采用访问策略优化输入输出端口的存储访问效率。与传统的FCFS调度方法相比,PIPO具有更高的带宽利用率和更低的输入输出端口瞬时带宽抖动。论文还介绍了在Altera FPGA上基于SopC(System on Programmable Chip)的网络处理器原型实现。该原型包含4个微处理器核,通过软件控制和协处理器加速可支持4个千兆以太网接口。利用该原型,论文对并行处理结构中的指令集扩充和协处理器共享机制进行了深入分析和探讨。同时对文中提出的F2CL调度算法等关键技术进行了验证。本文的工作对网络处理器的设计具有重要的指导意义。更多还原

【Abstract】 With the development of network applications, network devices need more intelligent processing capability. This requires network devices to have various functions (e.g. multi-layer switching, security processing and traffic management) as well as powerful protocol processing capability and programmability, so that the novel network services can be quickly deployed and configured in these network devices. Thus network processors (NPs) which are based on the technology of Application Specific Instruction Processor (ASIP) emerge timely and are widely used in network domains to meet these requirements. NPs have already become one of the core devices in the next-generation Internet.This dissertation focuses on the issues of system design and implementation of NPs. The early design method and performance evaluation of NPs are presented on the standpoint of system design, and several key implementation technologies of NPs are investigated in-depth in this dissertation. The main contributions of the dissertation are as follows:(1) Aiming at the optimal decision and performance evaluation of system design in NPs, the YinHe Network Processor Design Framework (YH-NPDF) is constructed according to the characterization of Multi-Processor System on Chip (MPSoC) design and requirements of network packet processing. The YH-NPDF is based on the idea of platform-based design. It adopts the Reactive Dataflow Process Network (RDPN) model to describe network applications and establishes the parameterized model of NPs’ hardware resources, where application model is mapped into the parameterized architecture model of NPs to evaluate the NP performance. The global annealing genetic algorithm is used to accelerate the search of design space and to optimize the design decision of NP system. The YH-NPDF can be used to model network applications and hardware resources and support optimal decision to meet the requirements for intelligent packet processing in early system design of NPs.(2) In network processors based on parallel processing elements (PEs), a packet parallel scheduling algorithm based on Fuzzy Feedback Control Loop (F2CL) is proposed. This algorithm uses F2CL schemes to improve the degree of load balancing among multiple processing elements, and also deploys a flow cache to buffer the scheduling information of packet streams. The packet reordering is effectively controlled by using the following two methods: when the workloads among PEs become unbalanced, the algorithm prefers to adapt the heavy-loaded flows; the successive packets belonging to the same flow can be remapped to another PE in case of flow timeout. The simulation results show that this algorithm with the well-chosen design parameters can gain preferable effects on packet ordering while preserving load balancing, and has better overall performance on load balancing and packet ordering when compared with other algorithms.(3) Based on the characteristics of the packet buffer memory in NPs, a multi-channel packet buffer memory system with the scheme of Pipelining Input and Parallel Output (PIPO) is proposed. PIPO schedules the write-required sequence with pipelining on the input and processes the read-required sequence in parallel on the output. Both actions in PIPO use memory access policy to improve the effectiveness of memory access. The effectiveness of PIPO, adaptive capacity of variable packet length and extensibility of buffer bandwidth are evaluated by theoretical analysis and simulation experiments with extrapolated workloads. Compared with traditional memory scheduling schemes of packet buffering such as FCFS, PIPO gains better effectiveness of memory access and higher utility ratio of buffer bandwidth, meanwhile incurs less jitters of instantaneous bandwidth on both inputs and outputs.Furthermore, the prototype system of network processor based on SoPC (System on Programmable Chip) is implemented on Altera FPGA. Four soft processor cores (i.e. Altera Nios II) are embedded into the prototype chip which can support four 1000Mbps Ethernet interfaces through co-processor acceleration under software control. Instruction set extension and co-processor sharing schemes for parallel processing architecture of NPs are analyzed and evaluated in depth in the prototype. Meanwhile, the F2CL-based packet scheduling algorithm is verified. The work in this dissertation can serve as an important guideline for the design of NPs.更多还原