【作者】 季爱明；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2006， 博士

【摘要】 可重构计算作为一种新的高性能计算解决方案,它具有较高的性能和灵活性,是通用处理器和ASIC的折衷。由于具有较高的灵活性,可重构计算的设计空间巨大,为某个特定的应用领域设计一个优化的可重构计算体系是一项十分复杂的任务。在可重构计算体系设计初期,搜索可重构计算体系的设计空间,选择一个优化的可重构计算体系是一项十分重要的研究工作。本文研究了二维阵列型可重构计算的设计空间搜索方法。 为了使设计空间搜索方法不依赖于任何具体的可重构计算体系,本文定义了描述可重构计算体系的结构特征参数,并提出了可重构计算体系的层次型参数模型。层次型参数模型既能反映可重构计算体系的结构特征,又能反映可重构计算体系的层次性。层次型参数模型具有良好的灵活性,能够描述不同类型的二维阵列型可重构计算体系。由于在高层次对可重构计算体系的结构特征进行数学抽象,层次型参数模型能够提高可重构计算体系的设计空间搜索速度。 在可重构计算设计空间搜索过程中,应用领域中的每个算法对可重构计算体系的互连资源提出了不同的需求。论文研究了可重构计算体系的互连资源估计问题。在建立应用算法网表布线随机模型的基础上,提出了基于随机模型的可重构计算体系的互连资源估计方法,从而能够估计应用领域中的各个算法在可重构计算体系上实现时所需要的各种互连资源的数目,确定了可重构计算体系的互连资源。 可重构功能处理单元阵列是可重构计算体系的核心部件。论文研究了可重构功能处理单元阵列的设计空间,推导了可重构功能处理单元阵列的面积、性能和功耗的估计公式。通过分析应用算法的变换方法、应用算法在可重构计算体系上的执行模型以及性能估计方法,给出了性能约束的可重构功能处理单元阵列设计空间搜索方法,从而使可重构计算体系的设计空间搜索方法能够跨越静态可重构计算体系和动态可重构计算体系,并能够在满足应用算法性能约束的前提下,为应用领域中的算法搜索一个最优的可重构功能处理单元阵列。 存储器结构是可重构计算体系的重要组成部分,其影响应用算法在可重构计算体系上的执行时间。论文讨论了存储器结构的设计空间搜索方法,研究了存储器结构中局部数据存储器容量、配置上下文存储器容量和局部数据存储器与可重构功能处理单元阵列之间的接口带宽,推导了局部数据存储器容量和配置上下文存储器容量的最大值以及局部数据存储器与可重构功能处理单元阵列之间接口带宽的最大值,最后提出了面积约束的存储器结构设计空间搜索方法,在搜索域选择性能最优的存储器结构。更多还原

【Abstract】 Reconfigurable computing is a new paradigm for current high performance computing, which promises an intermediate trade-off between Application Specific Integrated Circuits (ASICs) and general purpose microprocessors. It provides powerful flexibility and performance. Because of its flexibility, reconfigurable computing architecture (RCA) has a vast design space, and it is a hard task to develop an optimized RCA for application specific domain. It exists very high value to search the design space of RCA and guide its design at an early stage. The dissertation emphasizes on the method for two dimension array based RCA design space exploration.In order to make design space exploration method independent on any concrete RCA, the dissertation defines a set of architectural parameters, which characterize different RCA. Based on it, hierarchical parameter model for RCA is presented, which not only characterizes RCA, but also describes the architecture’s hierarchy. It has powerful flexibility, and can describe different two dimension array based RCA. Because mathematical abstraction for RCA is at high level, hierarchical parameter model accelerates RCA design space exploration.During design space exploration, each algorithm makes a different demand on connection resources of RCA. Connection resources estimation for RCA is discussed in the dissertation. By establishing stochastic model for application algorithm net routing, a method for estimating RCA connection resource based on stochastic model is given. It gives the number of each connection resources for application algorithm which is implemented on RCA, and the number of connection resources of RCA is determined.Reconfigurable processing element array is a key component in RCA. With analyzing reconfigurable array design space, the dissertation explains the algorithm to estimate area, time and power for reconfigurable array. By studying transformation, executing model and executing time of application algorithm, an algorithm with performance constraint for reconfigurable processing element array design space exploration is proposed. The algorithm produces the best reconfigurable processing element array for application domain, which meets the performance expectations of application algorithm.Memory architecture is an important component in RCA. Finally, the method for memory architecture design space exploration in RCA is discussed. The dissertationgives the maximum for local data memory size, configuration context memory size and the bandwidth of interface between local data memory and reconfigurable array. An algorithm with area constraint for memory architecture design space exploration is proposed, which acquires memory architecture with the best performance for application domain.更多还原