【作者】 曹克；

【导师】 汪蕙；

【作者基本信息】 清华大学 ， 电子科学与技术， 2005， 博士

【摘要】 随着无线通信和CMOS工艺的发展,采用CMOS工艺实现射频通信电路和系统成为合理的选择。这样的混合信号系统要求前端电路能够在低电压下工作。同时,现代射频通信前端尤其是LNA必须具有低噪声、高线性,在低功耗的条件下实现这些要求是实现射频通信系统关键技术之一。本论文研究了低电压、低功耗CMOS低噪声放大器(LNA)的设计,包括以下内容:1.对短沟道MOSFET电路仿真模型在特定运用状态下(强反型饱和区)进行简化,提出了一个简化设计模型以及通过电路仿真和数据拟合提取模型参数的方法。用这个方法可以推出MOSFET的大信号、小信号和噪声模型,用来分析预测电感源极负反馈LNA的增益、噪声、线性度和功耗,减少设计迭代次数。2.分析了0.18微米工艺下MOSFET中各种噪声对于电感源极负反馈LNA噪声系数的影响,得到了计算噪声系数的解析式,并由此得出结论,由于寄生电容的作用,LNA的噪声系数依然主要决定于沟道热噪声电流;因此适当设计输入跨导级MOSFET的尺寸,可以实现低功耗低噪声。设计了一个低电压的折叠结构电感源极负反馈共源共栅LNA,仿真验证了上述结论。3.应用级数展开的方法分析了电感源极负反馈LNA的非线性,得到了LNA线性度和功耗关于栅源偏置电压和MOSFET尺寸的解析表达式。为了获得高的线性度,有必要采取补偿的办法。比较了各种非线性补偿方法,提出了一种低电压的用线性区MOSFET补偿来提高线性度的折叠型电感源极负反馈共源共栅LNA,给出了该电路的设计原则。流片测试结果证明了采用这种按照这个原则设计的补偿结构电路能够以较小的功耗代价将输入三阶交截点功率提高约5dB。4.解析分析了封装寄生效应对源极电感负反馈LNA各项性能的影响。指出在给定封装寄生参数的条件下,为了保证LNA输入端阻抗严格匹配以及高增益、低噪声,应当适当加大输入级MOSFET的栅源之间的电容。比较了两种加大电容的方法,指出适当加大MOSFET沟道长度的方法优于添加附加并联电容的方法。仿真验证了上述结论。更多还原

【Abstract】 With the development of radio frequency (RF) communications and the CMOStechnology, it has become a reasonable choice to implement the RF communicationcircuits and systems in CMOS process. The RF front-end circuits in this kind ofmixed-signal systems are required to be able to work under low voltage. Front-ends,especially LNAs for modern RF communications are also required to be low-noiseand highly linear and to fulfill those requirements with low power is among the keytechnologies for the implementation of RF communication systems.The design of low-voltage, low-power CMOS low noise amplifiers (LNA) isconducted in this thesis and includes:1. A simple design model and the method to extract its parameters by circuitsimulation and data fitting is proposed based on simplifying the circuit simulationmodel of short channel MOSFET in a specific operation region (strong inversion andsaturation). The large-and small-signal model, and noise model can be derived toanalyze the gain, noise, linearity and power of inductively source-degenerated CMOSLNAs and to predict their simulation results so that the design iterations can bereduced.2. The contribution of different noise components of MOSFETs in 0.18micrometer process to the noise figure (NF) of the inductively source-degeneratedLNA is calculated and the analytical expression of the NF is derived. It is shown thatdue to the parasitic capacitance NF is still dominated by the channel thermal noisecurrent;therefore, low noise can be achieved with low power dissipation by properlysizing the MOSFET in the input transconductance stage. A low-voltage foldedcascode inductively degenerated LNA is designed and the above analysis is verifiedby simulation.3. The nonlinearity of the inductively source-degenerated LNA is analyzed withseries expansion method and analytical expressions relating the power and linearity tothe size and bias of the MOSFET are found. Compensation is needed to achieve highlinearity, and different compensation methods are compared. A low-voltage foldedcascode LNA compensated using MOSFET in the triode region is proposed, and thenthe design guides are given. About 5dB input-inferred third-order interception pointpower enhancement at little power cost has been demonstrated by the measurementsof the fabricated IC chip compensated with this technique and designed under thegiven guides.4. The effects of packaging parasitics on the performance of inductivelydegenerated LNAs are analytically studied. It is shown that, with parasitics given, toachieve perfect input matching, high gain and low noise, the capacitance across thegate and source of MOSFET in the input stage should be properly large. Two ways toenlarge the capacitance are compared and using longer channel MOSFET ispreferable to adding an extra parallel capacitor. These observations are verifiedthrough circuit simulation.更多还原