【作者】 陈诚；

【导师】 任俊彦；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2005， 博士

【摘要】 随着数字化时代的到来,人们对以太网的数据传输率要求不断提高。现有快速以太网的10Mbps和100Mbps数据传输速率已不能满足许多应用的要求。因此,IEEE组织早在1996年就开始制订千兆以太网的相关传输标准,至1998年和1999年分别出台了基于光纤和5类非屏蔽双绞线的千兆以太网传输标准。 在基于5类非屏蔽双绞线千兆以太网模拟前端电路中,需要四个7—8比特分辨率、125MHz采样速率的高速模数转换器(ADC)把接收到的模拟信号转换成数字信号。而在便携式数字示波器中也能见到高速模数转换器的身影,其分辨率为8比特、采样速率在100MHz以上。同时,高速中等分辨率的模数转换器在液晶显示驱动、雷达、硬盘驱动电路等方面也有着广泛的应用。 作为混合信号系统芯片设计中的一个瓶颈,高速模数转换器消耗大量的芯片面积、功耗和设计时间。在众多种模数转换器电路结构中,折叠内插结构具有高速、低功耗、面积小及易与数字工艺兼容等优点。在90年代中期以前,折叠内插结构的模数转换器基本上都是用双极型工艺实现的。由于CMOS工艺的发展和设计技术的提高,现在用CMOS工艺实现的折叠内插模数转换器越来越多。随着集成电路朝SoC的趋势发展,要求模数转换器在系统芯片中嵌入化。尽管折叠内插结构模数转换器相对而言具有面积小的特点,但已有的研究结果显示,大多数的面积仍然在1mm~2左右或者更大,不利于模数转换器的嵌入式应用。 基于上述研究背景,本论文对用于千兆以太网全集成8比特分辨率、125MHz(可工作在200MHz)转换速率、小面积模数转换器进行了设计研究。主要工作如下: (1) 设计了一个独创的采用全晶体管实现的折叠电路。与传统的采用电阻负载的折叠电路相比,该全新的折叠电路完全用晶体管代替了电阻负载。在共模输出电压方面,全晶体管实现的折叠电路具有更好的电源电压抑制能力,而且没有采用电阻负载,折叠电路的共模输出电压以及增益对工艺的偏差并不敏感。因此,后级电路不必要求有很宽的输入范围,可以运用较简单的电路结构及较小的晶体管尺寸。晶体管负载相对于电阻负载占用的芯片面积更小。这些都有助于减小整个模数转换器的功耗和占用的面积。 (2)采用分布式采样保持电路。与单独的采样保持电路相比,分布式采样保持电路更适合于折叠、内插等结构的模数转换器,且对电容的线性度要求不高,可以用MOS管栅电容实现,节省面积。另外,除了时钟电路变复杂外,后者在线性区域、动态性能、功耗等方面都优于单独的采样保持电路,且可以与预放大电路结合在一起,使得折叠内插模数转换器的结构更紧凑。更多还原

【Abstract】 With the stepping into the digital era, there exists an increasing demand for data transmission rate by Ethernet. The 10Mbps and 100Mbps data transmission rate of the existing fast Ethernet can’t meet the requirements of many applications. Therefore, IEEE started the design of transimission standards concerned Gigabit Ethernet very early in 1996 and released the Gigabit Ethernet transmission standards with fibre and CAT-5 unshielded twisted-pair cabling respectively in 1998 and 1999.In Gigabit Ethernet based on CAT-5 unshielded twisted-pair cabling, the analog front-end transceiver needs four 7 to 8-bit ADCs having a sampling rate of 125MHz to convert the received analog signal to digital data 8-bit ADCs with sampling rates above 100MHz can be found in portable digital oscilloscopes, too. Furthermore, high-speed moderate-resolution ADCs are required widely in applications such as LCD driver, radar, hard disk driver.As a bottleneck in the mixed-signal system design, high-speed ADC consumes a large chip area, power budget and designing period. Among a lot of ADC architectures, folding and interpolating technology possesses advantages of high speed, low power, small chip area, easiness to be compatible with digital process, etc. Most of the folding and interpolating ADCs were realized in bipolar process before the mid 90s. With the development of the CMOS process and design technique, more and more folding and interpolating ADCs are realized in CMOS technology now. The evolution for System-on-Chip (SoC) requires an ADC embedded i n a system chip. Though folding and interpolating ADC has a comparably small chip area, the reported research results show that nearly all occupy an area of about 1mm2 or above, which is not appropriate for embedded applications.Based on the above researchs, this dissertation focus on the design of an 8-bit 125-MSPS (also OK for 200-MSPS) small-area ADC used in Gigabit Ethernet. The main contri butions can be concluded as folIowi ng:(1) A novel transistor-only folder is designed. Compared with a conventional folder with resistive loads, the novel folder replaces the resistive loads completely with transistors. The transistor-only folder has a better power-supply rejection capability regarding the common-mode output voltage. Without using resistive loads, the common-mode output voltage and the gain of the proposed folder are insensitive to the process variations. The更多还原