【作者】 于春利；

【导师】 郝跃；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2005， 博士

【摘要】 轻掺杂漏（LDD）工艺已经成为亚微米、超深亚微米MOS器件能够有效地抑止热载流子（HC）效应的标准工艺之一，但它同时也带来了在小尺寸器件模型和热载流子退化机理方面与常规结构器件的差异。本文针对超深亚微米漏工程器件的模型及可靠性的研究，建立了适用于超深亚微米LDD NMOSFET器件的Ⅰ-Ⅴ简捷模型并改善了衬底电流模型的描述。对实验数据的参数提取方法也进行了修正，使提取出的参数更符合实际情况。对热载流子的特殊退化机理从实验和理论两方面进行了详细研究，证实了超深亚微米LDD NMOSFET器件的两阶段退化机理。对低工作电压下的碰撞电离机理进行了较深入的分析，并且验证了在0.18微米CMOS工艺中EES效应和晶格温度升高带来的碰撞电离热助效应的存在，提出了在低电压下器件最坏热载流子应力条件转换的微观机理，并阐述了它们与器件热载流子寿命的关系。主要研究结果如下： 首先通过分析总结典型的短沟MOS器件模型的建模原理和适用范围，建立了适用于深亚微米、超深亚微米LDD NMOSFET的简捷器件模型（Compact model）。模型采用了双曲正切函数的经验描述方法，包括了对反型状态和亚阈状态的描述，结合短沟器件载流子速度饱和理论，充分考虑了各种短沟效应的影响因素。广泛采用理论分析和实验数据相结合的方法，对器件的阈值电压、输出特性、跨导特性、衬底电流等进行了解析分析，使模型的计算简便，且保证一定的精度。 重点分析了衬底电流的机理，在Ⅰ-Ⅴ特性模型的基础上建立了适用于LDD NMOSFET的短沟衬底电流半经验—半解析模型，其中对特征长度l这一非常重要的参数做了改进描述，使之更适合分析薄栅深亚微米器件的衬底电流特性，该模型被用于从亚微米到超深亚微米的LDD NMOSFET的性能描述，得到了与实验数据相一致的模拟结果。 设计并采用0.18微米CMOS工艺制造了LDD NMOSFET器件样品，对传统的参数提取方法进行了改进，提取出了与栅偏压和器件尺寸相关的参数，如阈值电压、源漏串联电阻、有效迁移率、有效沟道长度等等，这些参数的变化规律符合LDD器件的特殊工作机理，并应用到已经建立的器件模型中进行了验证分析，结果显示器件的输出电流特性、跨导特性、转移特性和衬底电流特性等的模拟与测试数据达到了很好的一致性，证明了参数的精确提取对器件建模的重要作用。 通过对自主设计的0.18微米CMOS器件工艺的LDD NMOSFET管芯进行的大量不同的HC应力测试，根据其阈值电压的漂移特点和线性漏电流的退化特性以及饱和趋势，证明了此阶段大多数界面损伤发生在质量较差的侧墙中，随后有更多的负电荷累积在栅—漏重叠区（亚扩散区）及沟道区，进一步证实了热载流子两阶博十论文:超深亚微米LDD MOSFET器件模型及热载流子可靠性研究段退化理论模型。得到具有氧化物侧墙的LDD NMOSFET器件所呈现的两个不同退化阶段的不同机理:第一阶段，侧墙下LDD区漏串联电阻的增加;第二阶段，主要是沟道中迁移率的减小。提出可靠性评估标准。 通过实验的方法验证了超深亚微米LDD NMOSFET的最坏热载流子应力条件的转变，分析了沟道长度、漏电压和温度在决定最坏热载流子应力条件中的作用。研究表明，最坏热载流子应力条件，是器件沟道长度、漏电压以及温度的函数。随着超深亚微米NMOSFET器件尺寸的缩小和电源电压的降低，EES效应和自热效应这样的能量获得机制，对其HC退化的影响越来越大，是出现非幸运电子模型效应的根本原因。 对影响最坏热载流子应力条件的因素进行了深入分析，得出沟长的减小和温度的降低均会促使最坏热载流子的栅压应力条件转变。最坏栅压应力条件从IsuB，MAx（D AHC）转变为Vds=Vgs（C HC），使加速热载流子应力下的器件寿命预测理论需要重新修正。对于某些沟长的器件，栅压应力IsuB，^DAHC和Vds二Vgs（C HC）下的器件寿命曲线有交叉现象，因此对于器件的最坏应力条件的评估，不能只在每个应力条件下仅仅考察一个漏偏置电压。 分析了EES效应对低工作电压下的碰撞电离的增强作用。研究表明，电子能量分布（EED）中的高能尾的存在，使EES效应对碰撞电离率M的影响在低温下更明显。栅压vG的增大，使EES比率增加，引起M的增大。在MOSFET中，电子的大部分能量是从高场区获得，因此，高能尾中的电子总数不仅依赖于电子的密度，而且还与器件高场区的电场强度有关。在特定VD下随着LG的减小，漏端的电场增强，EES效应增强。因此，对于低工作电压下抑止热载流子效应的超深亚微米器件的设计，特别是应用于低温环境中的器件设计，EES效应的影响是不可忽视的。 分析了晶格温度对超深亚微米LDD NMOSFET低工作电压下的碰撞电离的增强作用。晶格温度引起的碰撞电离热助效应的研究表明，电子能量分布中的热尾与晶格温度的关系，使低漏电压下的碰撞电离率对于温度的增加更加敏感，晶格温度升高效应增强。随着电源电压等比例降至1 .2V以下，碰撞电离的产生因素从电场转变为晶格温度，自热效应会促使这个问题更加严重。而栅偏压较高时，低漏压下的碰撞电离热助特性可以被EES效应所掩盖。 这些在建立适用于深亚微米、超深亚微米LDD NMOSFET的器件模?更多还原

【Abstract】 Hot carrier effect has a significant impact on submicron and deep-submicron scaling down MOSFET. The lightly-doped-drain (LDD) is an efficient process to improve hot carrier immunity of MOSFET. However, the parasitic series resistance and parasitic capacitance caused by the lightly doped region in the source/drain can reduce the drain current drive and the high frequency performance. The features such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), velocity saturation, etc, are of some difference from the features in conventional short channel devices, thus increasing the complexity of the MOSFET modeling.In this work, one emphasis is put on the nonlinear modeling of LDD MOSFET, wherein the drain current Ids is the key of the MOS equivalent circuit. A semi-empirical model of DC I-V characteristics for ultra-deep submicron LDD MOSFET is proposed by employing empirical hyperbolic tangent description and theory of carrier saturated-velocity under high electric field. The model deals with the I-V characteristics in either strong inversion or subthreshold region. Also the smooth transition between linear and saturation region is guaranteed by th(x) description, avoiding the discontinuity of drain conductance. The parasitic resistance due to the lightly doped region is treated as an external parameter. Because the substrate current in LDD MOSFET still demonstrates an unique characteristics different from the conventional MOSFET, particularly in the very short gate length devices, and it is very sensitive to the hot carrier degradation, a novel substrate current model which is different from that for conventional S/D device is proposed for submicron and deep-submicron lightly-doped-drain (LDD) n-MOSFET, with the emphasis on the description of an important parameter - characteristics length l, which takes into account the effects of channel length and bias. The maximum lateral electric field Em, the length of velocity saturation region ld which are very sensitive to drain current and substrate current are significantly affected by this parameter. The substrate current model can be easily embedded in the model to match the related device measurement and explore the hot carrier degradation of the deep submicron devices. The modeling of the device is based on the methodology for the physical model and the empirical model, thus decreasing the computation consumption, maintaining the accuracy, and clarifying the mechanism of devices. The comparison between simulations and measurements for submicron and deep submicron LDD MOSFETs shows an excellent agreements.Further more, the accuracy of some parameters, such as the threshold voltage,drain-source parasitic resistance, the effective channel length, and the effective mobility, etc., is of great importance in the device’s model. So we propose a novel parameters extraction method suitable for short channel length LDD MOSFET’s. By subsection of the total gate bias range, the linear regression yields the gate bias independent parameters Rds, △L and μeff in a very small gate bias range. The repeat extraction operations in different subsections obtain the accurately gate bias dependent parameters in the total bias range. The method avoids the gate bias range optimization, retains the accuracy and simplicity of the linear regression extraction. The parameters are extracted from the measurements of the different gate lengths LDD NMOSFETs fabricated on 0.18μm CMOS technology, and as validity, are implemented in the compact I-V model. The excellent agreements between simulations and measurements indicate the effectivity of this technique.Another emphasis is on the different degradation behavior of ultra-deep submicron LDD NMOSFET from the conventional devices. Under the different stress conditions , including channel hot-carrier (CHC) stress and drain avalanche hot-carrier (DAHC) stress, the output drain current, the threshold voltage, the transconductance, the substrate current, the lifetime, etc., show the self-limiting time-dependent HC degradation, suitable更多还原