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ATLAS液氩量能器一期升级前端触发电子学原型系统研究

The Development of Front End Trigger Electronics Prototype System in ATLAS LAr Calorimerers Phase-I Upgrade

【作者】 胡雪野

【导师】 安琪; 陈虎成;

【作者基本信息】 中国科学技术大学 , 物理电子学, 2014, 博士

【摘要】 超环面仪器实验装置(ATLAS)是欧洲核子研究中心大型强子对撞机的七大探测器谱仪之一。它利用大型强子对撞机LHC(Large Hadron Collider)空前的高质心对撞能量等优越实验条件,着力于研究希格斯玻色子、β衰变中的CP破坏线索以及Top夸克属性等未知的物理现象。ATLAS在2012年夏天探测到的希格斯玻色子(125GeV)无疑带给世界一个振奋人心的好消息。为了进一步提高ATLAS研究潜力并满足更广泛的物理需求,ATLAS合作组决定提升探测器的硬件性能,并随之制定了“ATLAS三期逐步升级”方案。其中,“一期升级”要求ATLAS探测器在更高亮度、更严重的堆积噪声环境中仍需保持100kHz触发带宽,这个挑战使探测器的升级以及新触发读出系统的研制都迫在眉睫。本论文以介绍ATLAS液氩量能器一期升级的前端电子学系统设计背景为出发点:首先提出了液氩数字化触发系统的可行性研究方案;然后介绍了液氩数字化触发系统中核心器件的选型以及各器件独立测试模块的设计及评估(电气性能和耐辐照性能);进而详细说明了1/4液氩数字化触发原型系统的整体设计以及其测试系统的搭建、测试结果的分析;最后简要介绍液氩数字化触发验证系统的设计并展示最新测试结果。论文的组织按章节如下:第一章介绍了粒子物理实验中量能器的重要作用。首先简要介绍了量能器的主要类型、适用领域及新型量能器的研发。然后概括了量能器的电子学特点及发展趋势。最后详细描述了ATLAS液氩量能器的结构以及其电子学系统设计需求。第二章阐述了ATLAS液氩量能器一期升级的总体背景。首先简要介绍了LHC以及ATLAS探测器的结构以及升级的总体规划,然后分析了一期升级的物理需求。本章的最后部分明确了ATLAS液氩量能器一期升级的目的以及与二期升级的兼容性。第三章介绍了ATLAS液氩量能器的当前电子学系统。首先展示了液氩量能器的当前粒度分布及信号特征;然后简要介绍了当前触发读出电子学系统的设计需求、总体结构以及各子模块功能;最后讨论了当前电子学系统的局限性及升级目标。第四章探讨了液氩数字化触发系统LTDB (Liquid Argon Trigger Digitizer Board)设计方案的可行性。首先简介了LTDB升级背景并提出LTDB的设计要求:每块LTDB不仅需要对320通道细粒度“超级信息胞”(‘’Super Cell",SC)信号进行40MHz的数字化采样并进行数据封装后通过光纤传输到后端电子学系统,而且需要重新将“层累加模块”输出的累加信号进行层与层之间的二次累加并将结果返回给“触发塔形成模块”,以保证当前的触发电子学系统仍可以正常工作。然后从以下方面讨论了LTDB的研制重点:主要包括机械设计、散热系统设计、供电电源设计、模拟电路和数字电路如何分离以及核心元器件的选择和评估,同时本章还给出为LTDB制定的分阶研制计划。第五章描述了1/4液氩数字化触发原型系统的整体设计。该系统包括:1/4数字化触发母板(处理80通道的“SC”信号)、模拟信号调理子模块、光纤子卡系列以及模拟信号注入模块。同时,本章还重点描述了以上各子模块的原理性设计以及版图规划。最后本章详细阐述了1/4液氩数字化触发原型系统的测试,包括测试系统的搭建、测试类型以及测试结果。第六章介绍了液氩数字化触发验证系统。该系统主要包括:全尺寸数字化触发母板(处理320通道的“SC”信号)、模拟信号调理子模块(v2.0)、PPOD子卡系列(v2.0)、QSFP子卡以及LTDB机械验证模块。本章简要说明了液氩数字化触发验证系统的整体设计并展示了液氩数字化触发验证系统的最新测试结果。第七章总结全文,并展望未来工作。

【Abstract】 ATLAS is one of the seven particle detector experiments constructed at the Large Hadron collider (LHC), a particle accelerator at CERN in Switzerland. The experiment is designed to take advantage of the unprecedented energy available at the LHC and investigate many different types of physics that might become detectable in the energetic collisions of the LHC, like the improved measurement of the Higgs boson, the possible clues for CP violation, the properties of the top quark, etc. In July2012, ATLAS is one of the two LHC experiments involved in the discovery of a particle consistent with Higgs boson, which is great news to the world. In order to extend and support the ATLAS physics reach, the ATLAS collaboration has devised a staged program in three phases. The Phase-I upgrades require ATLAS to keep the100kHz trigger bandwidth with increased luminosity and more severe "pileup". In this case, the development of new detector and readout components are needed, which is also the primary motivation of the Phase-I detector upgrades.Based on the design of front end electronics in ATLAS LAr calorimeter Phase-I upgrade, we discuss the following key points in this thesis. Firstly, we explore the feasibility of the LAr Trigger Digitizer Board (LTDB) and propose a "step-by-step" development plan. Then, we introduce key parts evaluation, and their test boards design as well (check both electronics function and radiation performance). Next, we detailed explain the design of quarter-slice LTDB prototype system and the set up of its test system. We also analyze the test results. In the last part, we briefly present the development of LTDB demonstrator and show its latest test result. This thesis is arranged as follows.In chapter1, we illustrate the importance of calorimeter applied in partical physics. First of all, we show different categories of the calorimeter and explain their application field. Also, we discussed the R&D of new types of calorimeter. Then we summarize the features and the trend of the calorimeter electronics. At last, we describe the structure of ATLAS LAr calorimeter and the requirement of its electronics design.In chapter2, we present the general background of ATLAS LAr calorimeter Phase-Ⅰ upgrade. Firstly, we explain the structure of LHC and ATLAS detector and show their upgrade plans up to2030and beyond. Then, we give physics requirements of the Phase-Ⅰ upgrade. Finally, we discuss the objectives of the Phase-Ⅰ LAr upgrade project and the compatibility with Phase-Ⅱ upgrade.In chapter3, we give an overview of the existing readout and trigger system. We show the granularity distribution of the calorimeter and the detector signal features at the beginning. Then, we briefly introduce the design parameters, general structure and sub-modules’function of the existing readout electronics system. At last, we discussed the limitations of the existion LAr electronics and give the upgrade objective of the current readout and trigger system.In Chapter4, we discuss the feasibility of different LTDB design schemes. Based on the Phase-Ⅰ upgrade background, we give the following features of the LTDB baseline design:Each LTDB will process up to320fine granularity "Super Cell" signals, includs sampling "SC" signals at40MHz, packaging digital "SC" signals and sending them to the back end digital processors via optical fiber. It also forms the legancy trigger signals (layer sum signals) and sends them to the TBB (Tower Builder Board) to keep the current analog chain unaffected. Then, we focus on the development of LTDB, which basically consists of the following aspects:the mechanical design, the power supply, the choice of form factor, the selection and evaluation of the key parts used on LTDB. In this chapter, it also makes a "step-by-step" implementation plan for LTDB.In chapter5, we present the quarter-slice LTDB prototype system. It consists of quarter-slice digital mother board (deal with80"SC" channels), analog mezzanine, optical mezzanine and analog injection board. Detailed description of the schematic design and PCB layout of each module is given in this chapter. Then, we discuss the test set up for the quarter-slice LTDB prototype system, and step-by-step evaluation test as well. At last, we show the test results of the quarter-slice LTDB prototype.In chapter6, we introduce the LTDB demonstrator system. It consists of full-size digital mother board (process320"SC" channels), analog mezzanine (v2.0), PPOD mezzanine cards (v2.0), QSFP mezzanine card and LTDB mechanical board. Finally, we briefly present the design of LTDB demonstrator system and show its latest test results.Finally, in chapter7, we conclude this thesis and summarize what have been achieved.

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