【作者】 林斌；

【导师】 谭年熊； 史峥；

【作者基本信息】 浙江大学 ， 电路与系统， 2013， 博士

【摘要】 近半个世纪以来,集成电路的发展一直按照摩尔定律给出的轨迹不断向前。然而,不断增大的芯片集成度和越来越小的特征尺寸要求,使得集成电路制造面临越来越严峻的挑战。幸运的是,人们的不懈努力和科学技术的发展,使得摩尔定律的有效性延续至今。分辨率增强技术(Resolution Enhancement Techniques, RETs)在亚波长光刻条件下的集成电路制造过程中起了关键作用,使得光刻技术的极限不断向前推进,目前可制造的最小特征尺寸已经达到光源波长的六分之一以下。基于模型的光学邻近校正技术(Model-based Optical Proximity Correction, MBOPC)是应用最为广泛的分辨率增强技术之一。它通过校正掩模图形来弥补光刻过程中的图形转移失真。随着工艺节点的推进,可制造性设计中的版图热点管理技术越来越受到业界的重视。它为电路设计者和制造者提供了设计规则检查(Design Rule Check, DRC)之外的另一种沟通途径。本文的工作集中在基于模型的光学邻近校正和版图热点管理这两个方面。在基于模型的光学邻近校正方面,本文提出了三种改进的光学邻近校正方法：稀疏矩阵式光学邻近校正算法。该算法利用光刻模型的卷积核,在多边形切分之后校正之前找出对光强采样点光强变化影响较大的小边,在矩阵式光学邻近校正计算雅可比矩阵时,只计算这些权重较大的小边对应的矩阵元素,以减小矩阵式光学邻近校正的计算量。该算法在保留了矩阵式光学邻近校正高精确度特性的同时,加快了校正速度。适用于图像传感器像素阵列的光学邻近校正方法.CMOS图像传感器像素阵列版图是由相同的像素单元(Cell)多次调用规则排列而成。像素单元在版图上通常是对称图形,对晶圆上制造结果的对称性要求也很高。针对图像传感器像素阵列的特点,我们提出的方法对其进行版图层次化处理,对对称的像素单元版图进行对称化切分和对称化校正,在保证光学邻近校正结果的一致性和对称性的同时提高了校正速度。针对一维版图的快速光学邻近校正算法。根据一维栅格化设计规则设计的一维版图,需要通过有选择地延长线端,加入虚拟线条,优化线端间隙分布,使其成为密集线图形,以提高版图的光刻友好性。线端间隙优化后的连线面积通常比实际连线面积大很多。但是我们真正关心的仅仅是实际连线版图的光刻结果。因此在进行光学邻近校正时,只需要对实际连线及与其相邻的延长部分进行校正,而对虚拟连线和不与实际连线相邻的延长部分,只需要进行经验化的固定移动即可。这种快速光学邻近校正方法,可以显著提高校正效率。在版图热点管理方面,本文介绍了一种热点管理流程并提出了一种热点分类方法：基于晶圆检查和设计版图模式识别的热点管理流程。该流程包括缺陷过滤、热点分类、热点危险度排序、热点库建立等步骤,能够对晶圆缺陷检查结果数据进行高效分析管理,给版图设计者提供有效反馈,指导版图设计和校正,避免同类缺陷重复出现,提高芯片成品率。基于高阶局部自相关和离散二维相关的热点分类。热点分类是热点管理流程中的一个重要步骤。本文提出的方法首先利用高阶局部自相关函数提取热点版图特征向量；然后利用主成分分析方法降低特征向量维度；接下来用低维的特征向量进行热点预分类；最后应用基于离散二维相关的方法进行热点细分类。该方法可以有效地对中心偏移条件下的版图热点进行快速分类。更多还原

【Abstract】 In the last half a century, the development of IC has been keeping its pace with Moore’s Law. Although the constantly increasing integration level of IC and the smaller and smaller critical dimension (CD) have brought daunting challenges to IC manufacturing, fortunately Moore’s Law is still valid because of the development of science and technology and people’s efforts. Resolution Enhancement Techniques (RETs) which make the available minimal CD nowadays smaller than1/6of the wavelength of illumination system play an important role in IC manufacturing under sub-wavelength lithography condition. Model-based Optical Proximity Correction (MBOPC) is one of the widely used RETs. It compensates pattern distortion during lithography by modifying mask patterns. As the technology node moves forward, hotspot management, one of Design for Manufacturability (DFM) techniques, gets more and more attentions. It provides another communication method between IC designer and manufacturer besides Design Rule Check (DRC). The work of this thesis focus on MBOPC and hotspot management.On MBOPC, three improved OPC methods are proposed in this thesis.A sparse matrix MBOPC algorithm. After fragmentation, we find out the "sensitive area" using lithographic model kernels. When the Jacobian matrix used in the matrix MBOPC is evaluated, only the elements that correspond to the segments in the sensitive area of every control site need to be calculated. The computations will be greatly reduced. This algorithm will speed up the matrix MBOPC process while maintaining high accuracy.An OPC method suitable for pixel array layout of image sensor. The layout of pixel array of CMOS image sensor is constructed by lining up the same pixel cell. The polygons in pixel cell layout are usually symmetric, therefore, symmetrical result is expected on the wafer. In the proposed method, we process the pixel array layout hierarchically, apply symmetrical fragmentation and symmetrical correction to the polygons. This method results in high correction speed and symmetrical OPC result. A fast OPC algorithm for1-D layout. For better lithography friendliness, the layout designed using1Dimensional Gridded Design Rules (1D GDRs) need to be optimized into dense lines pattern by line end extension, dummy insertion and gap distribution optimization. After optimization, the optimized wires coverage ratio to layout is much larger than the original wires. However, in the optimized layout, only the parts of original wires are the functional parts. With the proposed algorithm, during the model-based OPC process, most of the extended parts and dummies of the layout are excluded from correction with empirical fixed offsets to save run time, and only the functional parts of the layout and the extended parts adjacent to them will be corrected. This algorithm significantly improves the OPC speed. On hotspot management, a management flow and a hotspot classification method are discussed in this thesis.A hotspot management flow based on wafer inspection and pattern recognition. This flow includes following steps:defect filtering, hotspot classification, hotspot risk ranking, hotspot library building and hotspot pattern matching. It can analyze and manage wafer inspection result efficiently, and can provides informative feedback to the layout designer. The feedback will be used as guidance in layout design and modification to reduce defect and impove chip yield.Hotspot classification based on higher-order local autocorrelation and discrete2-D correlation. Hotspot classification is an important step of hotspot management. In the proposed method, firstly, we extract the features of the hotspot patterns using HLAC method. Secondly, the principal component analysis (PCA) is performed on the features for dimension reduction. Thirdly, the simplified low dimensional vector features of the hotspot patterns are used in the pre-clustering step. Finally, detailed clustering using pattern similarity calculated by discrete2-D correlation is carried out. The proposed method can classify hotspots under center-shifting condition effectively and speed up the classification process greatly.更多还原