【作者】 赵津晨；

【导师】 吴晓波； 严晓浪； 赵梦恋；

【作者基本信息】 浙江大学 ， 电路与系统， 2013， 博士

【摘要】 Delta-Sigma数据转换器具有转换精度高、硬件开销低等特点,十分适用于便携式医疗设备以及高性能音频信号处理等领域。然而其设计中尚有许多技术问题有待深入研究,尤其是现代CMOS工艺与数字技术的发展使得集成电路的电源电压不断降低,严重制约了模拟信号的动态范围,也使得数据转换器的高分辨率设计成为难点。同时,对于便携式设备而言,电池的续航能力始终是决定产品竞争力的关键技术之一,这也对数据转换器的低功耗设计提出了更大挑战。本文根据一些重要应用领域的要求,对高精度音频Delta-Sigma数据转换器的设计技术展开研究,重点围绕其低功耗与面积优化技术展开,主要内容与创新包括：1.针对植入式生物医疗装置如人工耳蜗等对音频Delta-Sigma ADC的低压超低功耗及微型化的设计要求,结合理论计算与建模仿真,对设计中诸多非理想因素展开深度分析,归结出一套Delta-Sigma调制器的完整设计流程,给出了符合要求的电路设计指标；采用开关型运放与运放共享技术实现了积分器的低功耗设计,并利用基于高密度电容阵列的改进型量化器结构实现了转换器面积的大幅度优化；提出一种无信号衰减二次相加策略,在低功耗实现调制器内部信号相加的同时,解决了传统开关电容型加法电路因电荷分配引入的信号衰减问题,有效降低了多位量化器设计难度；还提出一种分割两向移位数据加权平均(Data Weighted Averaging,DWA)技术,可在较低硬件开销下减小多比特转换器的非线性误差,并有效抑制传统DWA技术在低频激励信号时谐波失真的产生,提高了转换精度。提出的音频Delta-Sigma ADC原型在0.18-μm CMOS工艺下流片,测试结果显示其峰值信噪比为92.2-dB,动态范围为94.6-dB,在0.9-V电源电压下系统总功耗为164-μW,其中Delta-Sigma调制器的功耗仅为56-μW,品质因数达到42-fJ/转换步长。2.针对高性能便携式音频信号处理的需要,对于高精度音频Delta-SigmaDAC的面积优化与低功耗设计技术展开研究。提出一种改进型公用副表式消除算法用于DAC内插滤波器的系数优化,有效降低传统算法下系统实现的硬件开销与逻辑深度,优化了芯片面积；以全数字实现方式将分割两向移位DWA技术应用于多位量化Delta-Sigma调制器,改善模拟重构级的非线性失真,以合理的硬件开销有效提高转换精度；采用低功耗FIR/IIR混合型滤波器的全差分直接电荷转移型开关电容DAC构建模拟重构级,同时片上集成了后置平滑滤波器,有效提升转换器性能。实验与芯片测试结果显示,提出的音频Delta-Sigma DAC峰值信噪比达到102.2-dB,动态范围为103.6-dB,在1.5-V电源电压下系统总功耗仅为3.54-mW,利用较小的芯片面积实现了转换精度与功耗之间的良好均衡。更多还原

【Abstract】 Featuring high conversion precision and low hardware overhead, delta-sigma data converters are appropriate for portable medical devices and high performance audio signal processing. However, there are still many technical problems remain to be discussed, especially for that the rapid development of modern CMOS technology and digital electronics makes a trend that the supply voltage of the electronic system is consistently lowering. This trend restricts the dynamic range of the analog signal, and therefore makes the design of high precision data converters even more difficult.In addition, the long battery life is always of key importance to the portable equipment to enhance its core-competitiveness, which makes low-power design facing more challenges.According to the key requirements of some major applications, this dissertation deeply studied the design techniques of high-precision audio delta-sigma data converters, especially their power and chip area optimization. The major contents and innovation include:1. Aiming at the demands on low-voltage ultra-low power and miniaturization of the audio delta-sigma ADC applying to implantable biomedical devices such as cochlear implants, an improved design process of delta-sigma modulator was summarized based on theoretical calculations, modeling and simulation combining with the in-depth analysis of non-ideality factors in design. Based on it, the circuit specifications satisfying the requirements were finally determined. Switched op-amps and the op-amp shared techniques were used to achieve low-power integrators, and an improved multi-bit quantizer based on high-density capacitor array was employed to optimize the chip area. A novel two-step adding scheme was proposed to realize the internal signals summation and avoid the attenuation of the signal swing caused by charge sharing between two or more capacitors, and therefore the design specifications of multi-bit quantizer were simplified. The split-and-bidirectional-shift data weighted averaging (DWA) technique was proposed to eliminate the mismatch errors caused in the feedback DAC without introducing signal-dependent tones. The prototype ADC has been implemented in a standard0.18-μm process and measured to have92.2-dB peak SNR and94.6-dB dynamic range with20-kHz signal bandwidth. The power consumption is164-μW of the ADC at0.9V supply voltage, and58-μW of the modulator, which translates to a figure-of-merit (FoM) of42-fJ/step.2. According to the demands on audio signal processing of high performance portable devices, the research on low power and area-efficiency optimization of high precision audio-band delta-sigma DAC was carried out. An improved common subexpression elimination method, which decreased the hardware overhead and logical depth was proposed to implement the coefficients of the interpolator. The split-and-bidirectional-shift DWA technique was applied in full-digital form to eliminate the mismatch errors of conversion units in the reconstruction filter. A hybrid FIR/IIR based direct charge transfer (DCT) DAC was employed to build the reconstruction stage, combined with an on-chip smooth filter to improve the system performance. Experimental and test results showed that the peak SNR and the dynamic range of the prototype delta-sigma DAC are102.2-dB and103.6-dB respectively, and the power consumption is3.54-mW under a voltage supply of1.5-V. it has been proven that a favorable balance between the converting precision and the power consumption is achieved.更多还原