【作者】 王新胜；

【导师】 毛志刚； 喻明艳；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2014， 博士

【摘要】 深亚微米集成电路内互连线规模庞大，互连线之间的耦合众多，以至于互连线的等效电路系统规模通常达到数万至数十万阶，传统的电路模拟分析工具无法实现对如此大规模互连电路的有效仿真分析，因此大规模互连电路的快速分析，成为集成电路性能分析和优化需要解决的基本问题之一。同时互连寄生对集成电路性能有越来越大的影响，增加了集成电路设计的压力。互连性能优化技术，是解决互连问题的一种有效手段。因此本文主要从集成电路互连的模型降阶分析及互连性能优化技术两个方面进行研究。针对空间投影互连系统模型降阶方面的问题，分别提出了基于Krylov子空间广义逆降阶方法、基于群智能算法的结构保留降阶方法和基于广义结构保留的参数化降阶方法。在分析传统的正交投影降阶和斜投影降阶或Galerkin投影降阶和Petro-Galerkin投影降阶方法基础上，针对在给定Krylov投影矩阵V下如何找到最优的投影降阶状态变量问题，提出了Krylov子空间广义逆投影降阶方法，其满足最小范数最小二乘投影要求，在空间投影的意义上，这是相对较优的降阶结果。针对传统的结构保留降阶方法不能完全保留状态矩阵中电感关联矩阵子模块结构的问题，即有可能造成电感对地回路问题，提出基于群智能算法的结构保留降阶方法，其把互连系统结构保留降阶过程转化为固定结构的参数优化过程，通过现代粒子群优化算法进行优化降阶。在分析广义结构保留模型降阶方法特点和互连参数的局部均匀性特征的基础上，提出广义结构保留的参数化降阶方法，其利用通用的结构保留降阶方法有效的保留系统参数变化的概率特性。仿真结果证明了上述方法的正确性与有效性。最后，针对空间投影互连系统模型降阶的时域全局误差限问题，给出了4种时域误差限计算方法。针对正交函数近似互连系统模型降阶方面的问题，分别提出了加权自适应阈值小波插值点选择降阶方法和切比雪夫-小波降阶方法。在有理Krylov降阶方法基础上，针对传统固定阈值小波插值点选择方法的不足，提出加权自适应阈值小波插值点选择降阶方法，从仿真结果来看，其精度明显高于固定阈值小波插入点选择降阶方法。针对切比雪夫函数近似降阶方法局部精度不足和4阶B样条小波近似降阶方法速度过慢的缺点，提出了切比雪夫-小波函数近似降阶方法，其是充分利用了切比雪夫-小波函数的优点构造了一个兼顾降阶速度和降阶精度的正交函数近似降阶方法。从仿真结果来看，切比雪夫-小波降阶方法降阶速度明显高于4阶B样条小波降阶方法而与切比雪夫降阶方法相近，而精度方面明显优于切比雪夫降阶方法与4阶B样条小波降阶方法相近。针对互连系统电路级优化方面的问题，分别进行了参数变化下缓冲器插入和低功耗工艺变化不敏感电流模电路方面的研究。在参数变化下缓冲器插入方面，提出了基于高斯拟合的快速缓冲器插入方法，此方法主要采用高斯函数拟合插入互连线和插入缓冲器的联合概率密度函数，其有助于联合概率密度函数的求解和优化解方案的选取。仿真结果证明了这种方法的正确性和有效性。在电路层面还提出了一种替代缓冲器插入的低功耗工艺变化不敏感的电流模电路，此电路的核心为一个自偏置结构的偏置电路，其主要通过变化补偿的思想抑制工艺变化的影响，同时通过减少静态直流通路个数而降低自身功耗消耗。仿真与测试结果表明延时受工艺变化的影响很小，同时功耗得到有效降低。针对互连系统结构与系统级优化方面的问题，提出了一种基于数据总线特点的FV-BI总线编码电路，其能有效改善FV编码所不能改善的连续两次传递未编码数据总线上的开关活动。此编码电路主要采用时分复用和寄存器共用技术，有效降低FV-BI编码电路的额外电路开销，而很大程度地改善数据总线开关活动，在随机数据下相比FV总线编码能降低总线开关活动的26.4%。同时提出了一个可用于系统级时序分析优化的缓冲器模型和一种系统级互连时序快速分析优化方法,其不但能用于不变参数系统互连时序分析与优化，而且也能用于工艺变化下互连系统时序分析与优化,仿真结果表明其正确性与有效性。更多还原

【Abstract】 Interconnect system in VLSI is complexity, and the mutual coupling is large.So, the equivalent circuit of interconnect wire scale usually reaches tens ofthousands to hundreds of thousands orders. Tranditional circuit simulation tools cannot achieve the effective analysis on such a large interconnect circuit. Thus，It is thefundamental problem of performance analysis and optimization of IC to solve rapidanalysis of large-scale interconnect circuit. Moreover, interconnect parasitics haveincreasing influence on integrated circuit performance, which increases the ICdesign pressure. Interconnect optimization techniques are a kind of effective meanto solve the problem of interconnection. Hence, this thesis mainly studies twoaspects those are the integrated circuit interconnect model order reduction (MOR)analysis and interconnect performance optimizaiton technology.In space projection MOR aspect, we have proposed MOR method basedgeneralized inverse in Krylov sub-space, MOR method based swarm intelligencealgorithm, and parameterized MOR method based general structure preservingtechniques. On the basis of traditional orthogonal projection and oblique projectionor Galerkin space projection and Petro-Galerkin projection, we proposepseudo-inverse projection method in Krylov subspace, which satisfies minimumnorm least squares projection condition that is relative optimal reduced order resultin the sense of space projection reduced order. For traditonal structure preservingMOR problem that do not maintain the structure of inductance incidence matrix inreduced order process, we propose a MOR method based a swarm intelligencealgorithm that turns structure preserving reduced order process into parameteroptimiztion process and then optimizes it. On the basis of local uniformitycharacteristics of interconnect wire, we propose a parameterized MOR methodbased on general structure preserving techniques that can effectively retain theprobability characteristics of parameterized interconnect system. Simulation resultsprove the correctness and effectiveness of all above methods. Finally, For the globalerror bound prolem of space projection reduced order methods, we propose fourtypes of error bound calculation methods in time domain.In orthogonal funciton approximation reduced order aspect, we have proposeda weighted self-adaptive threshold wavelet for interpolation point selection MORmethod and a Chebyshe-Wavelet reduced order method. Weighted self-adaptivethreshold wavelet for interpolation point selection MOR method is on the basis ofrational Krylov MOR by weighted self-adaptive threshold wavelet method to selectrational frequency interpolation points. From simulation results, the precision of MOR based weighted self-adaptive threshold method is higher than man-madethreshold method. For Chebyshev function approximation reduced order precisionlimitation in local approximation and4-order B spline wavelet reduced ordermethod speed problem，we propose a Chebyshev-Wavelet MOR method that makesthe fullest use of Chebyshev-Wavelet function to construct wavelet functionexpansion MOR method, which considers reduced order speed and precision. Fromexperiment results, the speed of Chebyshev-Wavelet method is highe than4-order Bspline wavelet method and is same with Chebyshev method. While the precision ofChebyshev-Wavelet method is highe than Chebyshev method and is same as4-orderB spline wavelet method.For the circuit level optimization aspect of interconnect system, we havestudied a buffer insertion method in parameter variation condition and low powerprocess variation-insensitive current-mode signaling scheme respectively. Inparameter variation buffer insertion fact, we have propsed a probability methodbased on Gaussian fitting, which mainly used Gaussian function fitting the jointprobability density of inserting wire and buffer. From simulation results, we canprove the correctiveness and effectiveness of the method. In the low power andprocess variation-insensitive current-mode signaling scheme, we have proposed anew current-mode circuit that mainly used a biasing circuit based on self-biasstructure to maintain process variation robust by compensation strategy. Fromsimulation and testing results, we can prove that interconnect system delay onlychanges very little due to process variations, while the power of current-modecircuit is reduced effectively.For the structure and system level optimization aspect of interocnnect system,we have proposed a time division multiplexing FV-BI bus coder based on data buscharacteristics. FV-BI coder can effectively improve the switching activity of thecase that is consecutive transmiting two uncoding data in data bus. Due to usingtime-divison multiplexing technology, it only need to introduce one additionalsignal line. Moreover, it can employ small area and consume less power by usingregister sharing technology. From simulation results, we can conclude that FV-BIcan improve26.4%switching activity in random data than FV coder. Meanwhile,we also propose a system level buffer model and a fast speed timing analysisoptimization method which can be used in system level timing analysis andoptimizaiton in normal condition and process parameter variation condition.Simulaiton results prove the correctiveness and effectiveness of it.更多还原