【作者】 金林；

【导师】 陈军宁；

【作者基本信息】 安徽大学 ， 微电子学与固体电子学， 2012， 博士

【摘要】 闪存是当前非易失性半导体存储器市场上的主流存储器件。随着闪存进入20纳米工艺节点,基于传统浮栅结构的闪存技术正面临严重的技术挑战,如浮栅耦合、电荷泄漏、相邻单元之间的串扰问题等。因而,提出了能够解决以上问题的电荷分立俘获型存储器。这种电荷俘获存储器件的基本结构是由隧穿层、存储层和阻挡层等功能层构成。本论文主要针对当前电荷俘获存储器可持续性缩小过程中的低压和高可靠性的需求,对阻挡层的材料、结构、后处理方式进行了优化,以及提出了光照的方法更准确的测试电容结构中少子参与的速度特性。本论文首先介绍了如何优化阻挡层材料。由于采用传统的SiO2做阻挡层材料,不能满足器件持续按比例缩小的要求,因而,提出了引入高k阻挡层。首先阐明了引入高k材料做阻挡层的原因。这就是阻挡层采用高k材料,能使电场更多的叠加在遂穿层上,从而增大器件的编程擦写速度。同时,高k阻挡层和大功函数的金属电极一起能够有效的抑制擦除饱和现象。接着,介绍了各种高k阻挡层及其相应的存储器件的性能。接着介绍了如何优化阻挡层结构。一种是采用堆叠的高k阻挡层。这样可以兼具多种高k材料的优点。另一种是在阻挡层和俘获层之间插入siO2层。由于SiO2带隙宽,那么器件可以在不损失速度的前提下,极大的改善器件的保持特性。然后提出了对阻挡层中常用的Al2O3材料进行后处理优化。我们实验中发现英高温退火能有效降低Al2O3材料的缺陷密度,从而,改善电荷俘获型存储器件的性能。同研究发现退火气氛对MANOS器件也有明显的影响。最后,研究中发现在电容结构中少子参与的速度特性测试中引入光照。并基于弛豫时间模型,提取了光照和非光照下的时间常数,光照可以有效的减小时问常数。并且,光照能够增大器件的编擦速度,使器件的速度和晶体管的速度相一致。更多还原

【Abstract】 Currently, flash are the dominant memory devices in the non-volatile semiconductor memory market. As the flash involves in the20nm nodes, the flash technology based on the conventional floating gate faces the big challenge. There are issues such as the floating gate coupling, charge leakage, the disturbing between the adjacent cells and so on. Thus, the discrete charge trapping memory is proposed to replace the floating gate memory. The charge trapping memory is composed of the tunneling layer, the charge trapping layer and the blocking layer. In order to meet the requirements of low operation voltage and high reliability, the optimization of the blocking layer is investigated in terms of materials, structure and post processing. Also, illumination is introduced in the speed measurement that minority carriers take part in the capacitor structure.This paper first introduces how to optimize the blocking layer in terms of materials. Since the conventional SiO2material as the blocking layer cannot meet the scaling down requirement, the high k material is introduced. Firstly, why to introduce the high k materials in the blocking layer is introduced. The reason is that the use of high k material in the blocking layer leads to more electric field is applied to the tunneling layer, which results in faster program/erase speed. Meanwhile, the high k blocking layer along with the high work function metal electrode can effectively suppress the erase saturation. Then blocking layers with various high k materials are introduced. Second, how to optimize the blocking layer in terms of structure is introduced. One method is to use the stacked high k blocking layer, which could combines advantages of different high k materials. Another is to insert SiO2between the charge trapping layer and the blocking layer. Since the band gap of SiO2is large, the retention of the memory device can be greatly improved without degrading the speed. Third, how to optimize the Al2O3material in term of post processing technology is introduced. Our experimental results show that the high temperature post deposition annealing can reduce the trap density in Al2O3material, which can greatly improve the performance of the MANOS device. Meanwhile, it is also found that the annealing atmosphere has an obvious effect on the MANOS device. Finally, the illumination is introduced in the speed measurement under the condition that minority carriers take part in the program or erase. Based on a relaxation time model, the time constant in the dark and illumination is extracted. Illumination can reduce the time constant. And illumination increases the program or ease speed in the capacitor structure. It is found that the speed in the capacitor under illumination is comparable with that measured in the transistor structure.更多还原