【作者】 梁上泉；

【导师】 高明伦； 尹勇生；

【作者基本信息】 合肥工业大学 ， 电工理论与新技术， 2011， 博士

【摘要】 SoC时代，随着CMOS工艺演进，系统芯片集成的强烈需求给模数转换器的设计带来诸多挑战。器件按比例缩小和电源电压降低等因素带来了模拟电路的非理想效应显著、动态范围降低、功耗增加、带宽受限、稳定性变差及技术革新成本提高等问题。本论文研究高性能ADC的数字辅助设计技术，借助数字信号处理知识体系的完备性，利用大规模数字电路在工艺、面积和功耗上的优势，减轻高性能ADC存在于架构、工艺、性能、面积、功耗等多方面的设计约束，用附加的数字辅助电路换取模拟电路系统的性能提升。首先，系统地归纳了采用数字信号处理知识体系的数字辅助设计技术的普适体系架构、一般性设计原理和设计流程，并以伪随机序列注入后台数字校准技术作为数字辅助设计技术的代表性研究实例展开探讨。文中研究伪随机序列注入校准技术的系统架构、基础理论和算法优化，解决系统到电路各个层次的一系列关键技术问题，使伪随机序列注入校准技术能够消除电容失配、运放有限开环增益等主要非理想效应，具备实时连续校准功能以及对外界干扰和输入信号不敏感等特性。其次，针对伪随机序列注入后台数字校准技术校准速度缓慢的问题，在频率域定量分析校准算法，建立相关算法与功率谱的数学关系，提出了改善校准速度的有效方法是减小相关去干扰电压幅度的观点。以频率域分析的结论为理论依据，基于ADSC调制结构，提出了数字高有效位削减技术和可配置双转换技术，不同程度地降低相关去干扰电压的幅度，从而提高级间增益估计值的收敛速度，改善伪随机序列注入校准技术校准速度缓慢的问题。最后，研究并设计了采用数字辅助设计技术的流水线ADC关键电路，包括14位、100Msps的采样保持放大电路、带溢出检测的3.5位／级余量增益放大器、考虑伪随机序列注入的子模数转换器等。更多还原

【Abstract】 In SoC era, with the development of the CMOS process, the design of data convertersintegrated in the system chips is faced with unprecedented challenges brought in by scalingtheory and lower supply voltage, which result in more obvious nonideal effect, decreasedsignal dynamic range, increased power consumption, restricted signal bandwidth, instabilityand increased cost, etc. The thesis researches digitally assisted design technique for highperformance ADC. It can reduce design constraints of the high performance ADC existed inarchitecture, process, performance, area and power consumption with the aid of thecompleteness of digital signal processing knowledge and the advantage of large scaleintegrated digital circuits in the process, area and power, and then improve the performance ofanalog circuits.At first, this thesis summarizes the universal system architectures, general designprinciples and the design process of digitally assisted design technique adopting digital signalprocessing knowledge. Taking the pseudo-random sequence injected background digitalcalibration techniques as an example, thorough studies are put forward, including the basictheories and optimum algorithms of the digital calibration techniques and a series of importanttechnical problem from system level to circuit level. The digital calibration technique cancalibrate errors and eliminate non-ideal effects in a continuous way, and is not sensitive to theoutside interferences and the input signals.Secondly, aiming at the problem of slow calibration speed of the pseudo-randomsequence injected calibration techniques, the thesis then makes frequency domain analysis andbuilds the mathematics relationships between the correlation algorithm and the powerspectrum. The conclusion is drawn that the effective method improving the calibration speedis to decrease the amplitude of the correlated interference voltage. In order to quicken thecalibration speed, two fast calibration techniques of ADSC-modulation architectures areproposed on the basis of the frequency domain analysis, which are digital MSBs clippingtechnique and configurable double convsersion technique. Different techniques have differenteffect of reducing the amplitude of the correlated interference voltages and improving theconvergence speed of interstage gain.At last, the key circuits of the pipeline ADC with digitally assisted design technique aredesigned, including14bits100Msps sample-and-hold amplifer,3.5bits/stage MDAC withBi-direction overflow detection, sub-ADC with pseudo-random sequence injection, etc.更多还原