【作者】 何小威；

【导师】 张民选；

【作者基本信息】 国防科学技术大学 ， 电子科学与技术， 2011， 博士

【摘要】 当前,随着CMOS工艺尺寸的逐步缩小和芯片集成度的大幅提高,有线互连在延时、功耗等方面遭遇巨大挑战,已接近互连金属材质的极限。为解决这类问题,使用片上天线和电磁波进行传输通信的无线互连技术应运而生。这给日益困难的微处理器时钟分布带来了新的实现途径,采用无线互连方式进行时钟分布具有延时小、功耗低、节省金属资源且不需要调制机制等优点,不仅可解决当今微处理器的时钟分布问题,还可快速评估无线互连技术对未来IC发展的潜力。本文针对微处理器时钟分布的发展趋势和面临的挑战,基于片上天线的特性研究和无线互连技术,提出了高频全局时钟无线分布的改进系统结构及若干关键技术,采用CMOS工艺设计实现了无线时钟分布系统的关键电路模块,并进行了模拟实验验证。本文的主要工作和创新点如下:1.提出了一种面向微处理器的全局时钟无线分布系统的改进结构,包括片上折叠偶极天线对、时钟产生电路、接收放大及分频电路等。采用PLL产生高频全局时钟,保证了整个无线时钟分布系统的抖动性能。这种结构由于对片上天线进行了折叠处理,有效地提高了芯片的面积利用率。和传统的有线时钟分布系统相比,这种结构的无线时钟分布具有延时低、由工艺变异引起的静态偏斜与抖动小、与低频数字电路之间的相互影响小、不占用大量金属互连线资源等诸多优点。2.提出了改进片上天线传输增益的新技术,即在硅衬底和金属散热器之间插入一层薄的金刚石介质材料,使片上天线对的传输增益在较宽的频率范围内有了大幅提高。为了能在实际的无线互连系统中预测天线的传播性能,提出了基于金刚石介质的电磁波修正传播模型和可能的传播路径,并对引入介质前后的电磁波传播路径进行了对比和解释说明。以2mm长、30μm宽的片上线性偶极天线作为实验对象,使用HFSS模拟验证了所提新技术的正确性和有效性。同时研究了无线互连应用中集成天线的特性对于衬底电阻率、金刚石厚度、天线对间距以及插入不同介质材料等因素的依赖关系,得出了薄的金刚石介质和高电阻率的衬底对提高天线增益有利。3.提出了片上天线对传输增益大小及相位在金属干扰环境下的若干线性经验公式,并归纳总结了一套适用于无线互连的片上天线设计规则。由于片上天线并非工作于孤立的环境中,其周围可能存在各种各样的金属干扰源。本文对影响片上天线的芯片内金属结构和布局进行了划分,定性分析了金属互连线、电源网格、散热与封装金属以及金属哑单元(Dummy Fills)对片上偶极天线工作特性的影响,使用三维电磁场软件HFSS对集成偶极天线的传输增益、相位、阻抗及辐射特性所受各种类型的金属干扰进行了全面模拟与分析,得出的经验公式和设计规则可用来指导片上天线的设计和版图规划。4.采用0.18μm CMOS工艺设计实现了高性能锁相环、低噪声放大器和8:1分频器等关键电路模块。锁相环采用LC型振荡器实现,模拟相位噪声在3MHz频偏处达–116dBc/Hz,能够提供高质量的无线时钟发射源。面向超宽带(Ultra-Wide-Band, UWB)应用和无线时钟分布接收器分别设计实现了两款低噪声放大器:UWB LNA和无线时钟分布LNA。前者采用共栅共源级联结构在1.5GHz~5GHz频率范围内获得了几乎恒定的功率增益,后者将容性交叉耦合技术引入到高频(大于10GHz)低噪声放大器的设计中来,较好地改进了低噪声放大器的增益、噪声和线性度性能。此外,无线时钟分布LNA和片上接收天线之间还实现了阻抗共轭匹配,从而获得最优的功率传输和系统性能。8:1分频器采用源耦合逻辑(Source Coupled Logic, SCL)实现,能够快速、准确地对无线接收到的全局时钟进行分频,工作频率高达17GHz。5.基于相位合成的思想提出并实现了一套局部时钟50%占空比调节机制。调节电路模块全部采用纯数字方式实现。使用同步镜像延迟(Synchronous Mirror Delay, SMD)技术具有较强的抗工艺、电压和温度变化的能力,消除了其它调节方法中复杂的反馈环路,进一步提高了调节性能。模拟实验结果表明,该调节机制对占空比在10%~90%范围内的输入时钟能在4个时钟周期内完成调节,输出时钟占空比为50%±2%。综上所述,本文将基于片上天线的无线互连技术应用于微处理器时钟分布,设计实现了一种全局时钟无线分布系统。模拟结果表明,11GHz的全局时钟通过无线传输、接收与八分频后得到1.375GHz的局部时钟,模拟的偏斜和抖动性能都较为理想。本文的研究成果对于推进无线互连应用和新型时钟分布技术的发展具有一定的理论价值和工程实践意义。更多还原

【Abstract】 Nowadays, as CMOS technology scales gradually and chip integration grows rapidly, wired interconnection encounters great challenges in terms of delay and power consumption, which almost reaches the intrinsic limitations of metal materials. To solve these problems, wireless interconnect using on-chip antennas and electromagnetic waves for communication begins to emerge accordingly. Clock distribution implemented by wireless interconnect has the advantage of low delay and power consumption, saving metal and no need for modulation scheme, which turns to be a new solution for increasingly difficult clock distribution for microprocessors in the future. Therefore, wireless clock distribution not only handles clock distribution problem of microprocessors, but also can be possible to rapidly evaluate the potential of wireless interconnect for the developments of integrated circuits (ICs) in the future.According to the trend and challenges of clock distribution for microprocessors, an improved configuration for wireless distribution of high frequency global clock along with several key techniques are proposed in this thesis, based on the investigations of on-chip antenna characteristics and wireless interconnect technique. The critical components of wireless clock distribution system are also designed and realized in CMOS technology. Simulations are made to verify the whole proposed wireless clock distribution system. The main research achievements and innovations described in this thesis are summarized as follows:1. A modified configuration of wireless global clock distribution system for microprocessors is proposed, which consists of folded on-chip antenna pair, clock generation and receiving circuits as well as frequency divider. Phase-locked loop (PLL) is used to generate high frequency global clock, which ensures the performance of the whole wireless clock distribution system. This structure utilizes chip area effectively due to the folded on-chip antennas. Compared with conventional wired clock distribution systems, wireless clock distribution system with the proposed configuration has a lot of benefits, such as low delay, low static skew and jitter caused by process variations, less interference with low frequency digital circuits, no occupying metal layers, etc.2. A novel technique for improving on-chip antenna transmission gain is proposed. That is to say, a thin diamond layer is inserted between the silicon substrate and metal heat sink, which enhances the transmission gain of on-chip antenna pair greatly in a wide frequency band. In order to make antenna transmission performance predictable in real wireless interconnection systems, a modified electromagnetic wave propagation model involving a diamond layer and possible propagation paths are also proposed and compared with those of none dielectric situation. A 2mm long, 30μm wide linear on-chip dipole antenna pair is chosen for experimental object, simulations using HFSS are performed to verify the correctness and validity of this proposed technique. Meanwhile, the dependences of characteristics of integrated antennas applied for wireless interconnect on substrate resistivity, diamond thickness, antenna pair separation and dielectric variety have been studied. It is concluded that thinner diamond layer and higher resistivity substrate are helpful to improve antenna gain.3. Several experiential linear formulas for antenna pair gain and phase in interfering circumstances are proposed, and a set of design rules is concluded accordingly for on-chip antennas targeting wireless interconnections. As on-chip antennas do not operate in isolated surroundings, instead, various metal interfering sources possibly reside around them. In this thesis, these metal structures and placements are first classified, then the impacts of on-chip metal connective lines, power grids, heat sink along with packaging metals, and metal dummy fills on integrated dipole antenna characteristics have been investigated with qualitative analysis. Extensive simulations are performed by three-dimensional electromagnetic software HFSS to explore the interfering effects of various neighboring metal structures on the transmission gain, phase, impedance and radiation pattern for on-chip dipole antennas. Obtained experiential formulas and design rules can be used for guiding on-chip antenna design and its layout planning.4. Key circuits of wireless clock distribution such as high performance phase-locked loop (PLL), low noise amplifier (LNA) and 8:1 frequency divider have been designed and implemented in a 0.18μm CMOS process. PLL is realized using a LC oscillator, which can generate high frequency global clock with fine quality. The simulated phase noise achieves–116dBc/Hz at 3MHz frequency offset. A LNA for ultra-wide-band (UWB) application and a LNA for high frequency wireless clock distribution receiver have been both designed and realized. The former LNA employing common gate (CG) and common source (CS) stages achieves nearly constant power gain during 1.5GHz–5GHz, while the capacitive cross-coupling technique is introduced in the latter LNA for high frequency (above 10GHz) LNA design, remarkably improving LNA performance including gain enhancement, noise and nonlinearity reduction. Additionally, impedance conjugate matching is performed between the wireless clock receiver LNA and on-chip antennas. Therefore, optimal power transmission and overall performance are obtained. The 8:1 frequency divider is realized by source coupled logic (SCL), which can divide the received global clock rapidly and exactly. The maximum operation frequency of the proposed divider is up to 17GHz. 5. A 50% duty-cycle correction mechanism for local clock is proposed and implemented based on phase-blending. All circuits are realized in a purely digital manner. Higher reliability is achieved against process, voltage and temperature (PVT) variations due to the utilization of the synchronous mirror delay (SMD) technique. Moreover, the proposed correction mechanism eliminates complicated feedback loops often used in other correction methods, which further improves the correction capability. Experimental simulation results indicate that the correction operation finishes in only 4 clock cycles when the duty-cycle of input clock ranges from 10% to 90%, and the output local clock duty-cycle is 50%±2%.In summary, the wireless interconnect technique based on integrated antennas has been applied for clock distribution in microprocessors, and a wireless global clock distribution system is designed and implemented in this thesis. Simulated results show that the generated 11GHz global clock is first transmitted and received by on-chip antennas, then divided by eight to become 1.375GHz local clock with excellent skew and jitter performance. The achievements presented in this thesis have academic and practical values for advancing wireless interconnect applications and the developments of novel clock distribution techniques.更多还原