【作者】 李娅妮；

【导师】 杨银堂；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2010， 博士

【摘要】 随着各种电子设备和产品的快速发展,以及集成电路制造工艺的不断进步,开关电源已成为当今电子设备的研究热点之一,并影响着电子产品设计的成功与否。作为开关电源的主要控制技术之一,功率因数校正技术也在经历不断的改进,向着高效率、低成本、低功耗、以及轻薄小的方向发展。功率因数校正(Power Factor Correction, PFC)技术能有效抑制电网一侧的输入电流波形畸变,减小总谐波失真(Total Harmonic Distortion, THD),从而满足电网对开关电源功率因数及谐波含量日益严格的要求,特别是能够满足更多的便携式电子产品在小功率应用场合的普遍需求。本文首先对单级有源功率因数校正电路的工作原理和控制模式进行了较全面的论述。由于其低成本、低功耗的特点,单级有源PFC通常适用于中低功耗的便携式电子产品。接下来对单级Boost PFC转换器的拓扑结构、工作原理和稳定性进行了较为深入的讨论,包括电流连续导通模式(Continuous Conduction Mode,CCM)、电流断续导通模式(Discontinuous Conduction, DCM)、以及临界导通模式(Boundary Conduction Mode, BCM) Boost PFC转换器的实现方法及其工作原理。对单周期控制技术的非线性控制机理、工作原理、调制规律、以及不同工作模式(CCM、DCM、BCM)下单周期Boost转换器的稳定性进行了分析研究,提出了稳定性工作的条件。采用电压和电流双闭环反馈控制技术,实现单周期BCM PFC转换器的整流和稳压功能；根据环路稳定性特点,对电压控制环路和电流控制环路进行补偿;基于Simulink建立了单周期PFC转换器的高层次行为模型,仿真和测试结果验证了其正确性和可行性。基于SinoMos 1.0μm BiCMOS工艺,完成单周期临界导通变频PFC转换器的电路设计。基于双环最优控制模式,采用多矢量误差运放、可编程锯齿波振荡器、过零检测电路实现变频控制,有效减少整个电源系统在轻载与重载时的功率损失,以及导通损耗和噪声；去除复杂的模拟乘法器,简化了传统PFC控制电路的结构。系统采用的关键性技术如下：1)采用高阶曲率补偿带隙基准电压源。在一阶温度补偿的基础上,利用双极晶体管的电流增益β随温度呈指数变化的特点,对带隙基准进行高阶温度补偿,同时为了防止热振荡现象的影响,加入带热滞回功能的过温保护电路,极大的提高了带隙基准的稳定性；2)采用多矢量误差运放和可编程锯齿波振荡器,保证系统根据外接负载及时调整PWM开关频率,有效减少整个电源系统在轻载与重载时的功率损失,提高有用功率。仿真和测试结果表明,该PFC转换器能跟随负载变化调整工作频率,在变频模式与间歇模式之间进行转换,满足低压省电模式要求；3)采用过零电流检测电路实现电流环控制,通过控制开关管的开启时间实现单周期临界工作模式,减小导通损耗和噪声,避免出现较大的电流间隙,提高了功率因数,采用具有350mV滞回电压的迟滞比较器提高系统的抗干扰能力,增加峰值电流检测网络及前沿消隐电路,获得尽可能小的电流畸变；4)采用周期性自启动定时电路,以及在振荡器与辅助绕组之间加入分流电阻Rz,使系统能够根据输入线电压的变化,及时而准确地调整PWM开关信号的占空比,从而显著降低AC输入线电压过零点附近的交越失真现象。基于SinoMos 1.0μm BiCMOS工艺,对版图进行了物理实现,并对芯片总体布局布线中需要考虑的问题进行了详细的讨论,包括器件和单元电路的匹配性、关键路径的布线、电源和地线的隔离、串扰噪声和闩锁效应、以及ESD保护等。有效芯片面积为1.61mmm×1.52mm。基于SinoMos 1.0μm BiCMOS工艺,对整体电路进行了流片验证,测试结果表明：所设计的系统具有较好的功率因数校正功能,启动电流仅为36gA,稳定工作时电流为2.43mA,正常工作时的开关频率为5-6kHz, PF值为0.988,线性调整率小于1%,负载调整率为3%,THD为3.8%,效率为97.3%。所有数据表明,本文提出的单周期临界导通PFC转换器能够满足低压省电模式以及低零交越失真的设计要求,且结构简单,效率较高。该电路能够根据负载情况自动调整PWM开关频率,有效降低系统芯片所需的功耗。更多还原

【Abstract】 With the rapid development of various electric devices and products, as well as the successive advancement of the integrated circuit manufacturing process, the switching power device has become one of the research focuses on the electric devices, and furthermore it has decided the success of the electronic product design. As one of the main control techniques of the switching power, the power factor correction (PFC) technology is also undergoing constant improvement and developing toward the direction of high efficiency, low cost, low power, light weight and small size. PFC technology can effectively restraint the input current waveform distortion at the side of the grid, and minimize the total harmonic distortion (THD), thereby meeting the increasingly stringent requirements of power factor and the harmonic content for the switching power supply by the grid, especially meeting the demands of the low power application for the portable electronic products.In this paper, the operating principle and control pattern of the single-stage active power factor correction (APFC) circuit are discussed completely at first. For its advantages of low cost and low power consumption, the single-stage APFC is widely used in the moderate and low-power portable electronic products. Then the topological structure, operating principle and the stability of the single-stage Boost PFC converter are discussed more in depth, mainly including the current continuous conduction mode (CCM), the current discontinuous conduction mode (DCM), and the boundary conduction mode (BCM) Boost PFC converter.According to the discussion of the nonlinear controlling mechanism, the operating principle, the modulation pattern and the stability of different operating modes, involving CCM, DCM, and BCM, have been analyzed and discussed. At last the stability working condition of the one-cycle PFC converter is proposed. Using the voltage and current double closed-loop feedback control technique achieves the one-cycle boundary conduction mode PFC converter with the rectification and stability functions. According to the loop stability conditions the compensation networks of the voltage control loop and the current control loop have been built respectively. Based on Simulink tool the high-level behavior model of the one-cycle PFC converter has been established. The simulation and test results verify the correctness and feasibility of this model. A one-cycle control BCM variable frequency PFC converter circuit is implemented using SinoMos 1.0μm BiCMOS process. Based on the double-loop optimal control mode, the circuit introduces the multi-vector error amplifier, the zero-crossing detection and the programmable sawtooth oscillator in order to achieve the variable frequency control, which effectively reduces the power loss of the entire power system at light loads and heavy loads, as well as the conduction loss and noise, and removes the complex analog multiplier and so simplifies the conventional PFC control circuit. The key design techniques used in the proposed PFC converter are as follows:1) A high-order curvature-compensated bandgap reference is studied. Based on the first-order temperature compensation, utilizing the characteristics of a bipolar transistor current gainβexponentially changing with temperature changes, a high-order temperature-compensated bandgap reference is implemented. In addition, an over-temperature protection circuit with thermal hysteresis function to prevent thermal oscillation is proposed, which greatly improves the performance of stability of the bandgap reference.2) A multi-vector error amplifier and a programmable sawtooth oscillator are introduced in this paper in order to modify the PWM switching frequency according to the external loads by the system, thus reducing the power loss of the entire power system at light loads and heavy loads effectively and increasing the useful power. The simulation and test results show that the PFC converter could change the work frequency with the load changes, and transform between the variable frequency mode and the interval mode to meet the requirements of low-power electric-saving PFC converter.3) A zero-crossing detection circuit is applied to realize the current control loop, which control the switching turn-on time to achieve the one-cycle BCM operating mode and to reduce the conduction loss and noise, as well as avoiding large current gap and improving power factor. A hysteresis voltage amplifier with 350mV hysteresis voltage is employed to strengthen the anti-jamming capability of the system. A peak current detection network and a leading edge blanking circuit are used for the current distortion as small as possible.4) The periodic self-starting timer circuit, with the shunt resistor Rz attached between the oscillator and the auxiliary winding, enables the system to accurately regulate the duty cycle of the PWM switching signals in terms of the input ac line voltage timely, thereby reducing the zero-crossing distortion in the vicinity of the AC input voltage zero-crossing points significantly.Based on SinoMos 1.0μm BiCMOS process, the whole layout of the chip is realized. At the same time, some issues which should be considered about the overall layout routing are discussed in detail, including the matching of devices and unit circuits, the routing of critical paths, the isolation of power supply and ground, the crosstalk noise, the latch-up effect, and the ESD protection, and so forth. The active die area is 1.61mm×1.52mm.Based on SinoMos 1.0μm BiCMOS process, the entire circuit has been verified. The test results are as follows:the designed system has a good power factor correction function, its start current is only 36μA, the stable operating current is 2.43mA, the normal operating frequency is 5～6kHz, power factor is 0.988, the linear adjusting rate is less than 1%, the load regulation rate is 3%, THD is 3.8%, and the system efficiency is 97.3%. All these data indicate that the proposed one-cycle BCM PFC converter could meet the requirements for low power saving mode and low zero-crossing distortion, as well as a simple structure and high efficiency. The circuit could adjust the PWM switching frequency automatically according to the load changes, and reduce required power consumption of the system chip efficiently.更多还原