【作者】 范明俊；

【导师】 任俊彦；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2010， 博士

【摘要】 随着第三代移动通信(3G)网络的快速发展,通信终端产品和消费类电子产品需求剧增,应用于这些产品中的10至12位数十兆赫兹低功耗流水线模数转换器成为了国际学术界和工业界研究的热点。通常这类模数转换器作为重要的数模混合信号模块嵌入在整个应用系统的SOC上,需要能兼容数字工艺和数字系统的低电源电压,并且追求低功耗。本论文对流水线模数转换器进行了全面的分析,在先进工艺下从低电压、低功耗的角度对12位数十兆赫兹流水线模数转换器在系统层面和电路结构层面做了深入研究,主要研究内容如下：(1)提出了新型低功耗低电压两级运算放大器。它可以工作在1.2V甚至更低的电源电压下,在两级运算放大器的第一级和第二级都采用Class-AB技术,从而增大了压摆率和跨导,缩短了信号建立时间。在相同的功耗和负载情况下,新型运算放大器可以达到普通两级运放的两倍带宽。(2)采用了采样前端路径匹配电路,消减了无采样保持器情况下信号通路的不对称引起的非线性。提出采样前端时序产生电路,根据现有的时钟树结构,通过增加与门和输入两倍的采样频率时钟,可以精确实现前端时序,避免了采用传统时钟电路实现时反向器链太长、时间延迟不易控制、时钟抖动(Jitter)大的现象。(3)分析了65nm 1.2V CMOS先进工艺下,所出现的负偏置温度不稳定性(NBTI)、阱临近效应(WPE)和浅沟槽隔离(STI)应力效应等非理性因素及其对电路性能的影响。依据这些非理性因素的物理模型,研究了克服这些非理想效应的物理版图优化方案,提高了物理版图设计的可制造性和后仿真性能。(4)提出了改进型CMOS开关作为余量增益电路(MDAC)中信号通路开关,在低电压(1.2V)和相同尺寸下,改进型CMOS开关相比传统CMOS开关导通电阻要小50%。(5)采用了高性能低抖动的片上时钟驱动电路。利用测试板输入差分正弦波,再通过芯片内部的预防大电路产生时钟信号,这种方式抑制了共模抖动,时钟抖动可以达到0.5ps以下,并且可以通过设计、仿真预防大电路预估时钟抖动的大小。基于上述研究,本论文完成了两个低电压低功耗模数转换器设计实例：第一个是采用中芯国际集成电路制造有限公司(SMIC) 0.13um 1.2V,单层多晶、八层金属混合信号CMOS工艺实现的12-B 40-MS/s流水线模数转换器,测试结果表明,在输入10.2兆赫兹信号下,此模数转换器的信噪失真比(SNDR)为60.2dB,信号噪声比(SNR)为60.5dB,无杂散动态范围(SFDR)可以达到78.2dB,总谐波失真可以达到-75.5dB,差分非线性(DNL)为±0.45 LSB,积分非线性(INL)为-6-4 LSB,在1.2V电源电压下功耗为15.6m,W；第二个是采用SMIC 65nm 1.2V单层多晶、七层金属、低泄漏CMOS工艺实现的12-B 50-MS/s流水线模数转换器,已送出流片,后仿真性能在TT 75°工艺角下SFDR为83.2dB, SNR为74.1dB, SNDR为73.4dB,有效位数(ENOB)为11.9位,在1.2V电源电压下,总体功耗为59mW。更多还原

【Abstract】 With the rapid development of the third generation mobile communication network, communication terminal products and consumer electronics products surge in demand, the low-power pipelined ADCs applied in these applications, with 10 to 12 bits and several tens of MHz, have become the international academic and industrial research focus. In general, this type of ADC, as an important mixed-signal module, is embedded in the SOC of the application systems. So this type of ADC needs to be compatible with digital CMOS process and low supply voltage, and lower dissipation. In this dissertation, the pipelined ADC is given with in-depth analysis, and from the low-voltage low-power point of view, the ADC with 12-B and several tens of MHz is given thorough studies at both the system level and circuit level, which includes(1) Two novel low-power low-voltage amplifiers are proposed and designed, which can work at 1.2V or even lower supply voltage. With the same load and dissipation, the novel amplifiers can provide two times GBW compared with the normal two-stage amplifiers by taking use of Class-AB technique in both stage 1 and stage 2, which enhances the slew rate and transconductance, and shorten the signal settling time.(2) A matching network in the sampling front-end is proposed, which can reduce the non-linearity caused by asymmetric signal path in case of no S/H module. A method to generate the timing of the sampling front-end is proposed. The precise front-end timing is realized by adding AND gate to the existing clock structure and inputting twice sampling frequency clock, which can avoid the phenomenon of much long inverter chain, difficulties of controlling the delay time and large clock jitter, caused by the realization with traditional clock circuits.(3) The negative bias temperture instability (NBTI), the well proximity effect (WPE), the shallow trench isolation (STI) stress effect and other non-ideal factors, are introducd, and the impact on the circuits from these effects are also given. According to the SPICE model of these effects, the layout solution for these effects is proposed, which improves the performance of the the design-for-manufacture (DFM) and the back-end simulation results.(4) The improved CMOS switches are proposed in the signal path of the MDAC. With the same voltage (1.2V) and size, the improved CMOS switches are with resistance which is 50% lower than that of the normal CMOS switches.(5) A high-performance low-jitter on-chip clock driver is used. The differential sine waves are required to be put into the chip and shaped by the on-chip pre-amplifying circuits to generate clock, by which the common-mode signal jitter is inhibited, and clock jitter can be reduced to 0.5ps or even lower. The clock jitter can be monitored by the back-end simulation. Based on the above research, two cases of low-voltage low-power ADC design are presented in the thesis. One is a 12-B 40-MS/s pipelined ADC based on SMIC 0.13-um 1.2-V 1P8M mixed signal CMOS process. The measured results show that the pipelined ADC are with 60.5-dB SNDR,60.2-dB SNR,78.2-dB SFDR,-75.5-dB THD,±0.45 LSB DNL,-6～4 LSB INL and 15.6-mW consumption under 1.2-V. the other is a 12-B 50-MS/s pipelined ADC based on SMIC 65-nm 1.2-V 1P7M, low-leakage CMOS process, which has been tapeout. The back-end simulation results show that the pipelined ADC are with 73.4-dB SNDR,74.1-dB SNR,83.2-dBSFDR,11.9-B ENOB and 59-mW dissipation under 1.2V supply voltage.更多还原