【作者】 王文廉；

【导师】 张波；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2010， 博士

【摘要】 现代电力电子技术的发展要求功率器件具有更优越的高压、高速、低功耗性能,超结(Superjunction,简称SJ)器件作为一类新型功率器件能进一步提高器件的耐压,降低比导通电阻。在超结MOSFET中,比导通电阻与耐压的1.3次方关系打破了常规器件中2.5次方的“硅极限”,缓解了比导通电阻与耐压之间的矛盾。LDMOS(Lateral Double-diffused MOSFET)是功率集成电路(Power Integrated Circuit,简称PIC)的关键器件,将超结技术应用于LDMOS构成SJ-LDMOS功率器件以提高其性能。但是,在横向超结器件中,纵向电场影响了超结的电荷平衡,使超结耐压下降,通常称为“衬底辅助耗尽效应”。这降低了SJ-LDMOS的性能,妨碍了横向超结功率器件的发展。本文研究了横向超结器件的耐压机理,通过优化体内电场分布,促进超结电荷平衡;并通过降低硅中的体电场提高器件纵向耐压,提出了横向超结器件的降低体电场(Reduced Bulk Field,简称REBULF)耐压模型。根据REBULF耐压模型,研制了一种基于电荷补偿的SJ-LDMOS器件,并从介质场增强和电位调节途径提出了两类新型器件结构,提高了横向超结器件的耐压。主要的创新工作包括: 1.提出了横向超结器件的REBULF耐压模型,通过优化体内电场提高超结器件的耐压。从电荷补偿、介质场增强和电位调节三个方面分析了优化体电场的方法。通过在漂移区补偿电荷来承担衬底耗尽,从而保证超结的电荷平衡,优化体电场;利用高密度的界面电荷增强介质层的电场,从而降低超结中的纵向电场,改善超结的电荷平衡,并提高器件纵向耐压;利用SOI器件的背栅特性,通过调节纵向电位,能优化体电场分布,促进电荷平衡。2.基于电荷补偿的REBULF耐压模型,结合BCD工艺的特点,研制了一种表面低阻通道LDMOS(Surface Low On-resistance Path LDMOS,简称SLOP LDMOS)。此器件利用高掺杂浓度的横向超结作为电流低阻通道,利用厚的N-well(或N-epi)作为纵向的耐压层,缓解了纵向电场对横向超结的影响,改善了电荷平衡,提高了器件耐压。同时,SLOP LDMOS利用了表面超结的特点,兼容了BCD工艺,能应用于功率集成电路。本文研制了500V耐压级的SLOP LDMOS器件,在超结宽度为3μm的情况下,测试的功率品质因数FOM (FOM = BV2/Ron,sp)达到了2.6MW/cm~2。3.基于介质场增强的REBULF耐压模型,提出了增强埋氧层电场的SOI SJ-LDMOS,包括具有埋氧层表面固定电荷和具有动态缓冲层的器件结构。通过界面电荷增强埋氧层的电场,降低了超结中的纵向电场,从而消除了纵向电场对超结电荷平衡的影响,同时提高了器件纵向耐压能力。动态缓冲层具有自适应增强电场的能力,利用电荷槽的电荷积累特性,电荷可以根据纵向电场的大小自适应的积累,做到了对电荷的按需分配,达到了完美的效果。分析表明,当漂移区长度为10μm时,超结器件的耐压达到220V,平均横向电场达到22V/μm。4.基于电位调节的REBULF耐压模型,提出了具有动态背栅电压的SOI SJ-LDMOS。利用SOI器件的背栅特性,通过动态的背栅电压来优化超结器件的纵向电场的分布。背栅电压使电子和空穴同时被吸引到埋氧层下方,这改善了超结的电荷平衡。因为背栅电压将一部分纵向电压从漏端转移到了源端,这提高了器件的纵向耐压能力。同时,本文还研究了基于电荷补偿的PSOI SJ-LDMOS。此结构利用超结在顶层形成低阻通道,降低比导通电阻。通过在漏端对埋氧层刻蚀,并增加N-buffer区,让衬底NP结参与耐压。这既补偿了超结的电荷,也解决了SJ-LDMOS的纵向耐压问题,同时保证了SOI的隔离优势。更多还原

【Abstract】 Modern power electronics technology requires power devices with superior performance in high voltage, high speed and low loss, super junction (SJ) device as a new type of power device can further improve the breakdown voltage (BV), reduce the specific on-resistance (Ron). For the SJ-MOSFET, the constraint relation between Ron and BV is improved form 2.5th power to 1.3th power, which breaks the“Silicon Limit”in conventional device, and improves the tradeoff between the BV and Ron. As SJ technology is applied in LDMOS (Lateral Double-diffused MOSFET), LDMOS, the key device in power integrated circuit, becomes SJ-LDMOS to improve the performance of device. However, the vertical electric field destroys the charge balance of SJ resulting in the low BV in the lateral SJ devices, which is called“substrate-assisted depletion effect”. This effect reduces the performance of SJ-LDMOS, and embarrasses the development of lateral super junction power device.In this dissertation, REBULF (Reduced Bulk Field) technology for the lateral SJ device is proposed by analyzing the breakdown characteristic of device. Optimizing bulk field can promote the charge balance of SJ, and reducing the electric field in bulk silicon can increase the vertical BV. According to the REBULF technology, an SJ-LDMOS based on charge compensation is investigated and implemented experimentally, and two new structures are presented basing on enhanced dielectric electric field and adjustable potential, which improves the BV of lateral SJ device. The detail contributions of the dissertation are listed as followings:1. REBULF model for lateral SJ power device is proposed to improve the BV by optimizing bulk field. The field is optimized by these three methods: compensating charges, enhancing dielectric electric field, and adjusting potential. First, added compensation charges in drift region take on the vertical depletion, which ensures the charge balance in SJ and optimizes the bulk field. Second, the electric field in dielectric layer is enhanced by high density interface charges, which reduces the vertical electric field in SJ, improves the charge balance of SJ, and increases the vertical BV of device. Third, the vertical potential is adjusted by utilizing specific back-gate character of SOI device, which optimizes the bulk field distribution and promotes the charge balance.2. Basing on charge compensation REBULF model, the surface low on-resistance path (SLOP) LDMOS is researched and implemented experimentally. A heavily doped SJ region provides a low on-resistance path in this device, and then thick N-well or N-epi layer sustains vertical voltage, which reduces the affect of vertical field on lateral SJ and improves the charge balance resulting in increased BV. In addition, SLOP LDMOS can be applied in power IC for compatible BCD process because the SJ is shallow on the surface of device. A 500 V class SLOP LDMOS is implemented in a BCD process. The experiment result shows a power figure of merit (FOM, FOM = BV2/Ron,sp) of 2.6 MW/cm2 , when pillar width is 3μm.3. Basing on enhanced dielectric electric field REBULF model, two kinds of SJ-LDMOS with enhanced electric field in BOX are proposed, which are with added fixed charges at surface of BOX and with dynamic buffer layer. Enhancing electric field in the BOX by interface charges reduces the vertical electric field in SJ, which eliminates the affect of the vertical electric field on the SJ charge balance, while the ability of the device vertical BV is increased. Dynamic buffer layer has the ability to adaptively enhance electric field. According to the characteristic of charges accumulation in the trenches, charges can be accumulated with the longitudinal electric field magnitude and distributed according to need, to achieve the perfect results. Simulation results show that the BV of the SJ device is to 220V, and the average lateral field is to 22V/μm, while the length of the drift region is 10μm.4. Basing on adjustable potential REBULF model, SOI SJ-LDMOS with dynamic back-gate voltage is proposed. Utilizing specific back-gate character of SOI device, the vertical electric field distribution in SOI SJ-LDMOS is optimized by dynamic back-gate voltage. Electrons and holes are attracted the bottom of the BOX to improve the charge balance. Due to partial vertical voltage transferred to source region from drain region, this increases the vertical BV.In addition, a new PSOI SJ-LDMOS with charge compensation has been studied in this dissertation. It reduces the specific on-resistance by low on-resistance path at the top of device with heavily doped SJ region. After etching buried oxide at the drain region to add an N-buffer region, the PN junction in substrate sustains more vertical voltage. It compensates the charges in SJ, increases the vertical BV, while preserves the isolation advantage of SOI device.更多还原