【摘要】 为了采用行为级模型来模拟结构复杂的ADC变换器的电气性能,本文提出了一种流水线ADC的行为级建模设计。首先提出流水线ADC行为级建模设计采用开关电容器电路构建,它由任意级联的k级流水级、前端采样保持(S/H)电路和数字校正逻辑构成,并给出了它们的具体模块电路实现及行为级模型;然后通过考虑流水线ADC的各种非理想特性如运算放大器的非理想特性参数(白噪声、有限直流增益、有限带宽、转换速率和饱和电压)、开关的非理想特性和采样时钟抖动,提出了实现这些非理想特性的行为模型。最后采用一个10位流水线ADC在Matlab Simulink中对其理想和非理想建模设计的仿真结果表明,本文提出的流水线ADC的行为级建模设计及其各个构成模块的非理想特性建模是精确和可行的。更多还原

【Abstract】 In order to use behavioral models to simulate the electrical performance of complex structured ADC converters,a behavioral level modeling design for pipelined ADC is proposed in this paper. Firstly,the proposed pipelined ADC behavioral modeling design is constructed using switched capacitor circuits,which is composed of an arbitrary cascade of k pipeline stages,a sample-and-hold( S/H) circuit at the front and digital correction logic,and the concrete realization of their module circuits and their behavioral level models. And then by considering various pipelined ADC non-idealities,such as operational amplifier non-ideal parameters( white noise,finite DC gain,limited bandwidth,slew rate and saturation voltages),the non-idealities of switchs and sampling clock jitter,the behavioral models to realize these non-idealities are presented. Finally,the simulation results for the ideal and non-ideal modeling designs of a 10-bit pipelined ADC in Matlab Simulink show that the proposed behavioral level modeling design for pipelined ADC and the modeling for non-ideality of each constructive module is accurate and feasible.更多还原